Clock & Control SLAVE, CPLD code

Logic comprised of two Mach5 CPLDs. All firmware for these was developed using MachXL V6.22 and Minc's Design Synthesis Language (DSL) and downloaded to the devices via JTAG using VantisPro software. Documentation here includes the DSL source (.src file), the physical information (.pi file), and the generated documentation (.doc file).

1. PLD1, VME interface (Mach5-128/120-7YC)
   • Source (.src file)
   • Pin definitions (.pi file)
   • Generated documentation (.doc file)

    

2. PLD2, GFLT interface (Mach5-512/184-7HC)
   • Source (.src file)
   • Pin definitions (.pi file)
   • Generated documentation (.doc file)

    

DAH / 3 Mar 00