PLDocument: Y:\clock\zeus\master\pld4\pld4.doc TITLE PAGE Tue Feb 29 15:25:56 2000 A MACHXL6.2.1.11 - (c) Copyright MINC Incorporated 1987-1998 ============================================================================== TITLE : ZEUS MVD C&C MASTER, PLD4: Clock Synchronisation FILE : Y:\clock\zeus\master\pld4\pld4 DATE : Thu Jun 04 02:36:00 1970 ENGINEER : Martin Postranecky / Dominic A Hayes COMPANY : University College London ============================================================================== MODULES : Document Generator 3.70 File Handler 6.2 Language Compiler 3.83 Architectural Optimizer 3.110 Device Lib Scan 3.2 Device Library 3.17 Device Partition 3.21 Device Fusemap 3.4 SWITCH VALUES : (Value in parenthesis represents batch mode switch value) PLCOMP PRODUCT TERM LIMIT : 128 PLOPT PRODUCT TERM LIMIT : 128 PLOPT REDUCTION : Espresso (1) NODE GENERATION : Procedure Instantiation Arithmetic and Relational Operators (1) PLDocument: Y:\clock\zeus\master\pld4\pld4.doc EQUATIONS Tue Feb 29 15:25:56 2000 EQUATIONS FOR SYSTEM INPUT SIGNALS (101) : envar_trig s_trig ext_trig vtrigger nclk_4 nclk_5 clk_6 noa_rst s_rst vmoa_reset vcalibrate cctdl[5..0] vf_error vbusy verror va_reset nenh_a_reset vt_error ext_error next_error vh_reset nenoa_rst acceptout rosysout_s34[1..0] entestbusy abortout clrtestbusy lbusy[5..1] lbusymask[5..1] lerror[5..1] lerrormask[5..1] lf_error[5..1] lf_errormask[5..1] ttypout_s24[2..0] seltt[2..0] ctpdl[15..0] testenout clk_1 wrcontr1 bcn0gflt neninitreset local_bcn0_s24 ttyp[2..0] rosys[1..0] s14[3..0] s34[0] OUTPUT SIGNALS (47) : trig_a trig_h ntrig_a cal_h oa_reset noa_reset cal_trig cal_busy ncal_busy f_errorout busy_1 nbusy_1 errorout t_errorout nerrorout h_reset not_reset busyout int_busy a_reset na_reset testbusy testpulse testcal_h a_accept trig_in initialise fltaccept fcstp mbusy merror mf_error testpulse_busy ntestpulse_busy testenclk1 acceptclk[3..1] a_abort local_mode gflt_mode init_reset ninit_reset da[1..0] lasttrig_abort m_busy_s34 PHYSICAL NODE SIGNALS (86) : f_err_and_busy.1.q1 f_err_and_busy.1.q3 cal_and_oa_rst.1.q1 cal_and_oa_rst.1.q2 cal_and_oa_rst.1.u cal_and_oa_rst.1.v cal_and_oa_rst.1.q4 cal_and_oa_rst.1.q5 cal_trig_delay.1.x cal_trig_delay.1.count[5..0] not_reset.1.q1 not_reset.1.q2 not_reset.1.q3 not_reset.1.q4 not_reset.1.q5 not_reset.1.q6 not_reset.1.q7 not_reset.1.w triggers.1.y triggers.1.z triggers.1.q0 triggers.1.q1 triggers.1.q2 triggers.1.q3h triggers.1.q4h triggers.1.q3a triggers.1.count[7..0] error_and_a_reset.1.q1 error_and_a_reset.1.q5 error_and_a_reset.1.q3 error_and_a_reset.1.q34reset busys.1.busy_count[3..0] busys.1.q1_reset busys.1.q2_reset busys.1.level_to_pulse.1.pulse busys.1.level_to_pulse.1.clr trigger_mpxers.1.q1 trigger_mpxers.1.q2 trigger_mpxers.1.q3 trigger_mpxers.1.q4 trigger_mpxers.1.q5 test_pulse_and_delay.1.q1 test_pulse_and_delay.1.q1_reset test_pulse_and_delay.1.testpulse_count[15..0] test_pulse_and_delay.1.equal_to-9 test_pulse_and_delay.1.equal_to-16 clocks.1.q1 clocks.1.q2 clocks.1.q3 clocks.1.q4 clocks.1.q5 mode_init.1.q4_reset select_lines.1.da_counter_clk select_lines.1.da_counter_reset last_abort.1.q3 last_abort.1.q_reset REDUCED EQUATIONS: trig_a.D = triggers.1.q3a ; "(1 term, 1 symbol) trig_a.CLK = nclk_4 ; "(1 term, 1 symbol) trig_a.RESET = /noa_rst ; "(1 term, 1 symbol) trig_h.D = triggers.1.q3h*/triggers.1.q4h ; "(1 term, 2 symbols) trig_h.CLK = nclk_5 ; "(1 term, 1 symbol) trig_h.RESET = /noa_rst ; "(1 term, 1 symbol) ntrig_a.EQN = /trig_a ; "(1 term, 1 symbol) cal_h.D = cal_and_oa_rst.1.q5 ; "(1 term, 1 symbol) cal_h.CLK = clk_6 ; "(1 term, 1 symbol) cal_h.RESET = /noa_rst ; "(1 term, 1 symbol) oa_reset.D = cal_and_oa_rst.1.q2 ; "(1 term, 1 symbol) oa_reset.CLK = nclk_5 ; "(1 term, 1 symbol) noa_reset.EQN = /oa_reset ; "(1 term, 1 symbol) cal_trig.EQN(~) = /cal_busy + cal_trig_delay.1.count[0]*/cctdl[0] + /cal_trig_delay.1.count[0]*cctdl[0] + cal_trig_delay.1.count[1]*/cctdl[1] + /cal_trig_delay.1.count[1]*cctdl[1] + cal_trig_delay.1.count[2]*/cctdl[2] + /cal_trig_delay.1.count[2]*cctdl[2] + cal_trig_delay.1.count[3]*/cctdl[3] + /cal_trig_delay.1.count[3]*cctdl[3] + cal_trig_delay.1.count[4]*/cctdl[4] + /cal_trig_delay.1.count[4]*cctdl[4] + cal_trig_delay.1.count[5]*/cctdl[5] + /cal_trig_delay.1.count[5]*cctdl[5] ; "(13 terms, 13 symbols) cal_busy.D = 1 ; "(1 term, 0 symbols) cal_busy.CLK = cal_h ; "(1 term, 1 symbol) cal_busy.RESET = /cal_trig_delay.1.x ; "(1 term, 1 symbol) ncal_busy.EQN = /cal_busy ; "(1 term, 1 symbol) f_errorout.D = f_err_and_busy.1.q1 ; "(1 term, 1 symbol) f_errorout.CLK = nclk_4 ; "(1 term, 1 symbol) f_errorout.RESET = /noa_rst ; "(1 term, 1 symbol) busy_1.D = f_err_and_busy.1.q3 ; "(1 term, 1 symbol) busy_1.CLK = nclk_4 ; "(1 term, 1 symbol) busy_1.RESET = /noa_rst ; "(1 term, 1 symbol) nbusy_1.EQN = /busy_1 ; "(1 term, 1 symbol) errorout.D = error_and_a_reset.1.q1 ; "(1 term, 1 symbol) errorout.CLK = nclk_4 ; "(1 term, 1 symbol) errorout.RESET = /noa_rst ; "(1 term, 1 symbol) t_errorout.D = error_and_a_reset.1.q5 ; "(1 term, 1 symbol) t_errorout.CLK = nclk_4 ; "(1 term, 1 symbol) t_errorout.RESET = /noa_rst ; "(1 term, 1 symbol) nerrorout.EQN = /errorout ; "(1 term, 1 symbol) h_reset.EQN(~) = nenoa_rst*/not_reset.1.q5* /not_reset.1.q7 + noa_rst*/not_reset.1.q5* /not_reset.1.q7 ; "(2 terms, 4 symbols) not_reset.EQN = /h_reset ; "(1 term, 1 symbol) busyout.EQN(~) = /local_mode*/m_busy_s34 ; "(1 term, 2 symbols) int_busy.D = 1 ; "(1 term, 0 symbols) int_busy.CLK = acceptclk[3] ; "(1 term, 1 symbol) int_busy.RESET = busys.1.q2_reset ; "(1 term, 1 symbol) a_reset.D = error_and_a_reset.1.q3 ; "(1 term, 1 symbol) a_reset.CLK = nclk_4 ; "(1 term, 1 symbol) a_reset.RESET = /error_and_a_reset.1.q34reset ; "(1 term, 1 symbol) na_reset.EQN = /a_reset ; "(1 term, 1 symbol) testbusy.D = 1 ; "(1 term, 0 symbols) testbusy.CLK = acceptclk[3] ; "(1 term, 1 symbol) testbusy.RESET = /busys.1.q1_reset ; "(1 term, 1 symbol) testpulse.EQN(~) = seltt[0]*/ttypout_s24[0] + /seltt[0]*ttypout_s24[0] + seltt[1]*/ttypout_s24[1] + /seltt[1]*ttypout_s24[1] + seltt[2]*/ttypout_s24[2] + /seltt[2]*ttypout_s24[2] + /testenclk1 ; "(7 terms, 7 symbols) testcal_h.EQN = /test_pulse_and_delay.1.equal_to-16* /test_pulse_and_delay.1.equal_to-9*testpulse_busy ; "(1 term, 3 symbols) a_accept.EQN = local_mode*trig_a + trigger_mpxers.1.q5 ; "(2 terms, 3 symbols) trig_in.EQN = local_mode*trig_h + trigger_mpxers.1.q2* /trigger_mpxers.1.q3 ; "(2 terms, 4 symbols) initialise.EQN = clocks.1.q2*rosysout_s34[0]* rosysout_s34[1] ; "(1 term, 3 symbols) fltaccept.EQN = clocks.1.q2*/rosysout_s34[0] + clocks.1.q2*/rosysout_s34[1] ; "(2 terms, 3 symbols) fcstp.EQN(~) = /cal_h*/testcal_h ; "(1 term, 2 symbols) mbusy.EQN = lbusy[1]*lbusymask[1] + lbusy[2]*lbusymask[2] + lbusy[3]*lbusymask[3] + lbusy[4]*lbusymask[4] + lbusy[5]*lbusymask[5] ; "(5 terms, 10 symbols) merror.EQN = lerror[1]*lerrormask[1] + lerror[2]*lerrormask[2] + lerror[3]*lerrormask[3] + lerror[4]*lerrormask[4] + lerror[5]*lerrormask[5] ; "(5 terms, 10 symbols) mf_error.EQN = lf_error[1]*lf_errormask[1] + lf_error[2]*lf_errormask[2] + lf_error[3]*lf_errormask[3] + lf_error[4]*lf_errormask[4] + lf_error[5]*lf_errormask[5] ; "(5 terms, 10 symbols) testpulse_busy.D = test_pulse_and_delay.1.q1 ; "(1 term, 1 symbol) testpulse_busy.CLK = clk_6 ; "(1 term, 1 symbol) testpulse_busy.RESET = /noa_rst ; "(1 term, 1 symbol) ntestpulse_busy.EQN = /testpulse_busy ; "(1 term, 1 symbol) testenclk1.EQN = /clocks.1.q1*testenout ; "(1 term, 2 symbols) acceptclk[3].EQN = /clocks.1.q3*a_accept ; "(1 term, 2 symbols) acceptclk[2].EQN = /clocks.1.q4*trig_a ; "(1 term, 2 symbols) acceptclk[1].EQN = acceptout*/clocks.1.q2 ; "(1 term, 2 symbols) a_abort.D = clocks.1.q5 ; "(1 term, 1 symbol) a_abort.CLK = nclk_4 ; "(1 term, 1 symbol) a_abort.RESET = /noa_rst ; "(1 term, 1 symbol) local_mode.EQN = wrcontr1 ; "(1 term, 1 symbol) gflt_mode.EQN = /wrcontr1 ; "(1 term, 1 symbol) init_reset.D = 1 ; "(1 term, 0 symbols) init_reset.CLK = initialise ; "(1 term, 1 symbol) init_reset.RESET = /mode_init.1.q4_reset ; "(1 term, 1 symbol) ninit_reset.EQN = /init_reset ; "(1 term, 1 symbol) da[1].D = /da[1] ; "(1 term, 1 symbol) da[1].CLK = select_lines.1.da_counter_clk ; "(1 term, 1 symbol) da[1].RESET = /select_lines.1.da_counter_reset ; "(1 term, 1 symbol) da[0].D = da[1]*/da[0] + /da[1]*da[0] ; "(2 terms, 2 symbols) da[0].CLK = select_lines.1.da_counter_clk ; "(1 term, 1 symbol) da[0].RESET = /select_lines.1.da_counter_reset ; "(1 term, 1 symbol) lasttrig_abort.D = a_accept ; "(1 term, 1 symbol) lasttrig_abort.CLK = abortout ; "(1 term, 1 symbol) lasttrig_abort.RESET = /last_abort.1.q_reset ; "(1 term, 1 symbol) m_busy_s34.EQN(~) = /busy_1*/testbusy*/cal_busy*/int_busy* /not_reset.1.q2 ; "(1 term, 5 symbols) f_err_and_busy.1.q1.CLK = nclk_4 ; "(1 term, 1 symbol) f_err_and_busy.1.q1.RESET = /noa_rst ; "(1 term, 1 symbol) f_err_and_busy.1.q1.D(~) = /mf_error*/vf_error ; "(1 term, 2 symbols) f_err_and_busy.1.q3.CLK = nclk_4 ; "(1 term, 1 symbol) f_err_and_busy.1.q3.RESET = /noa_rst ; "(1 term, 1 symbol) f_err_and_busy.1.q3.D(~) = /mbusy*/vbusy ; "(1 term, 2 symbols) cal_and_oa_rst.1.q1.D = 1 ; "(1 term, 0 symbols) cal_and_oa_rst.1.q1.RESET = /cal_and_oa_rst.1.u ; "(1 term, 1 symbol) cal_and_oa_rst.1.q1.CLK(~) = /s_rst*/vmoa_reset ; "(1 term, 2 symbols) cal_and_oa_rst.1.q2.D = cal_and_oa_rst.1.q1 ; "(1 term, 1 symbol) cal_and_oa_rst.1.q2.CLK = nclk_5 ; "(1 term, 1 symbol) cal_and_oa_rst.1.q2.RESET = /cal_and_oa_rst.1.u ; "(1 term, 1 symbol) cal_and_oa_rst.1.u.EQN = /oa_reset*noa_rst ; "(1 term, 2 symbols) cal_and_oa_rst.1.v.EQN = /cal_h*noa_rst ; "(1 term, 2 symbols) cal_and_oa_rst.1.q4.D = 1 ; "(1 term, 0 symbols) cal_and_oa_rst.1.q4.CLK = vcalibrate ; "(1 term, 1 symbol) cal_and_oa_rst.1.q4.RESET = /cal_and_oa_rst.1.v ; "(1 term, 1 symbol) cal_and_oa_rst.1.q5.D = cal_and_oa_rst.1.q4 ; "(1 term, 1 symbol) cal_and_oa_rst.1.q5.CLK = clk_6 ; "(1 term, 1 symbol) cal_and_oa_rst.1.q5.RESET = /cal_and_oa_rst.1.v ; "(1 term, 1 symbol) cal_trig_delay.1.x.EQN = noa_rst*ntrig_a ; "(1 term, 2 symbols) cal_trig_delay.1.count[5].CLK = clk_6 ; "(1 term, 1 symbol) cal_trig_delay.1.count[5].CE = cal_busy ; "(1 term, 1 symbol) cal_trig_delay.1.count[5].RESET = /cal_trig_delay.1.x ; "(1 term, 1 symbol) cal_trig_delay.1.count[5].XORL = cal_trig_delay.1.count[5] ; "(1 term, 1 symbol) cal_trig_delay.1.count[5].XORR = cal_trig_delay.1.count[0]* cal_trig_delay.1.count[1]*cal_trig_delay.1.count[2]* cal_trig_delay.1.count[3]*cal_trig_delay.1.count[4] ; "(1 term, 5 symbols) cal_trig_delay.1.count[4].CLK = clk_6 ; "(1 term, 1 symbol) cal_trig_delay.1.count[4].CE = cal_busy ; "(1 term, 1 symbol) cal_trig_delay.1.count[4].RESET = /cal_trig_delay.1.x ; "(1 term, 1 symbol) cal_trig_delay.1.count[4].XORL = cal_trig_delay.1.count[4] ; "(1 term, 1 symbol) cal_trig_delay.1.count[4].XORR = cal_trig_delay.1.count[0]* cal_trig_delay.1.count[1]*cal_trig_delay.1.count[2]* cal_trig_delay.1.count[3] ; "(1 term, 4 symbols) cal_trig_delay.1.count[3].CLK = clk_6 ; "(1 term, 1 symbol) cal_trig_delay.1.count[3].CE = cal_busy ; "(1 term, 1 symbol) cal_trig_delay.1.count[3].RESET = /cal_trig_delay.1.x ; "(1 term, 1 symbol) cal_trig_delay.1.count[3].XORL = cal_trig_delay.1.count[3] ; "(1 term, 1 symbol) cal_trig_delay.1.count[3].XORR = cal_trig_delay.1.count[0]* cal_trig_delay.1.count[1]*cal_trig_delay.1.count[2] ; "(1 term, 3 symbols) cal_trig_delay.1.count[2].CLK = clk_6 ; "(1 term, 1 symbol) cal_trig_delay.1.count[2].CE = cal_busy ; "(1 term, 1 symbol) cal_trig_delay.1.count[2].RESET = /cal_trig_delay.1.x ; "(1 term, 1 symbol) cal_trig_delay.1.count[2].XORL = cal_trig_delay.1.count[2] ; "(1 term, 1 symbol) cal_trig_delay.1.count[2].XORR = cal_trig_delay.1.count[0]* cal_trig_delay.1.count[1] ; "(1 term, 2 symbols) cal_trig_delay.1.count[1].D = cal_trig_delay.1.count[0]* /cal_trig_delay.1.count[1] + /cal_trig_delay.1.count[0]* cal_trig_delay.1.count[1] ; "(2 terms, 2 symbols) cal_trig_delay.1.count[1].CLK = clk_6 ; "(1 term, 1 symbol) cal_trig_delay.1.count[1].CE = cal_busy ; "(1 term, 1 symbol) cal_trig_delay.1.count[1].RESET = /cal_trig_delay.1.x ; "(1 term, 1 symbol) cal_trig_delay.1.count[0].D = /cal_trig_delay.1.count[0] ; "(1 term, 1 symbol) cal_trig_delay.1.count[0].CLK = clk_6 ; "(1 term, 1 symbol) cal_trig_delay.1.count[0].CE = cal_busy ; "(1 term, 1 symbol) cal_trig_delay.1.count[0].RESET = /cal_trig_delay.1.x ; "(1 term, 1 symbol) not_reset.1.q1.D = errorout ; "(1 term, 1 symbol) not_reset.1.q1.CLK = acceptclk[3] ; "(1 term, 1 symbol) not_reset.1.q1.RESET = /not_reset.1.w ; "(1 term, 1 symbol) not_reset.1.q2.D = not_reset.1.q1 ; "(1 term, 1 symbol) not_reset.1.q2.CLK = nclk_4 ; "(1 term, 1 symbol) not_reset.1.q2.RESET = /noa_rst ; "(1 term, 1 symbol) not_reset.1.q3.D = 1 ; "(1 term, 0 symbols) not_reset.1.q3.RESET = /not_reset.1.w ; "(1 term, 1 symbol) not_reset.1.q3.CLK(~) = errorout ; "(1 term, 1 symbol) not_reset.1.q4.D = not_reset.1.q3 ; "(1 term, 1 symbol) not_reset.1.q4.CLK = nclk_5 ; "(1 term, 1 symbol) not_reset.1.q4.RESET = /not_reset.1.w ; "(1 term, 1 symbol) not_reset.1.q5.D = not_reset.1.q4 ; "(1 term, 1 symbol) not_reset.1.q5.CLK = nclk_5 ; "(1 term, 1 symbol) not_reset.1.q5.RESET = /noa_rst ; "(1 term, 1 symbol) not_reset.1.q6.CLK = nclk_5 ; "(1 term, 1 symbol) not_reset.1.q6.RESET = /noa_rst ; "(1 term, 1 symbol) not_reset.1.q6.D(~) = /init_reset*/vh_reset ; "(1 term, 2 symbols) not_reset.1.q7.D = not_reset.1.q6 ; "(1 term, 1 symbol) not_reset.1.q7.CLK = nclk_5 ; "(1 term, 1 symbol) not_reset.1.q7.RESET = /noa_rst ; "(1 term, 1 symbol) not_reset.1.w.EQN = noa_rst*/not_reset.1.q5 ; "(1 term, 2 symbols) triggers.1.y.EQN(~) = /noa_rst + triggers.1.count[0]* triggers.1.count[1]*triggers.1.count[2]* /triggers.1.count[3]*/triggers.1.count[4]* triggers.1.count[5]*triggers.1.count[6]* /triggers.1.count[7] ; "(2 terms, 9 symbols) triggers.1.z.EQN(~) = /ext_trig*/s_trig*/vtrigger + /ncal_busy + m_busy_s34*/trig_a ; "(3 terms, 6 symbols) triggers.1.q0.RESET = /triggers.1.y ; "(1 term, 1 symbol) triggers.1.q0.D(~) = envar_trig*ncal_busy*/triggers.1.q0 ; "(1 term, 3 symbols) triggers.1.q0.CLK(~) = /cal_trig*/triggers.1.z ; "(1 term, 2 symbols) triggers.1.q1.D = envar_trig*triggers.1.z + triggers.1.q0 ; "(2 terms, 3 symbols) triggers.1.q1.CLK = nclk_5 ; "(1 term, 1 symbol) triggers.1.q1.RESET = /triggers.1.y ; "(1 term, 1 symbol) triggers.1.q2.D = triggers.1.q1 ; "(1 term, 1 symbol) triggers.1.q2.CLK = nclk_5 ; "(1 term, 1 symbol) triggers.1.q2.RESET = /noa_rst ; "(1 term, 1 symbol) triggers.1.q3h.D = triggers.1.q2 ; "(1 term, 1 symbol) triggers.1.q3h.CLK = nclk_5 ; "(1 term, 1 symbol) triggers.1.q3h.RESET = /noa_rst ; "(1 term, 1 symbol) triggers.1.q4h.D = triggers.1.q3h ; "(1 term, 1 symbol) triggers.1.q4h.CLK = nclk_5 ; "(1 term, 1 symbol) triggers.1.q4h.RESET = /noa_rst ; "(1 term, 1 symbol) triggers.1.q3a.D = triggers.1.q2 ; "(1 term, 1 symbol) triggers.1.q3a.CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.q3a.RESET = /noa_rst ; "(1 term, 1 symbol) triggers.1.count[7].CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.count[7].CE = trig_a ; "(1 term, 1 symbol) triggers.1.count[7].RESET = /triggers.1.q0 ; "(1 term, 1 symbol) triggers.1.count[7].XORL = triggers.1.count[7] ; "(1 term, 1 symbol) triggers.1.count[7].XORR = triggers.1.count[0]* triggers.1.count[1]*triggers.1.count[2]* triggers.1.count[3]*triggers.1.count[4]* triggers.1.count[5]*triggers.1.count[6] ; "(1 term, 7 symbols) triggers.1.count[6].CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.count[6].CE = trig_a ; "(1 term, 1 symbol) triggers.1.count[6].RESET = /triggers.1.q0 ; "(1 term, 1 symbol) triggers.1.count[6].XORL = triggers.1.count[6] ; "(1 term, 1 symbol) triggers.1.count[6].XORR = triggers.1.count[0]* triggers.1.count[1]*triggers.1.count[2]* triggers.1.count[3]*triggers.1.count[4]* triggers.1.count[5] ; "(1 term, 6 symbols) triggers.1.count[5].CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.count[5].CE = trig_a ; "(1 term, 1 symbol) triggers.1.count[5].RESET = /triggers.1.q0 ; "(1 term, 1 symbol) triggers.1.count[5].XORL = triggers.1.count[5] ; "(1 term, 1 symbol) triggers.1.count[5].XORR = triggers.1.count[0]* triggers.1.count[1]*triggers.1.count[2]* triggers.1.count[3]*triggers.1.count[4] ; "(1 term, 5 symbols) triggers.1.count[4].CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.count[4].CE = trig_a ; "(1 term, 1 symbol) triggers.1.count[4].RESET = /triggers.1.q0 ; "(1 term, 1 symbol) triggers.1.count[4].XORL = triggers.1.count[4] ; "(1 term, 1 symbol) triggers.1.count[4].XORR = triggers.1.count[0]* triggers.1.count[1]*triggers.1.count[2]* triggers.1.count[3] ; "(1 term, 4 symbols) triggers.1.count[3].CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.count[3].CE = trig_a ; "(1 term, 1 symbol) triggers.1.count[3].RESET = /triggers.1.q0 ; "(1 term, 1 symbol) triggers.1.count[3].XORL = triggers.1.count[3] ; "(1 term, 1 symbol) triggers.1.count[3].XORR = triggers.1.count[0]* triggers.1.count[1]*triggers.1.count[2] ; "(1 term, 3 symbols) triggers.1.count[2].CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.count[2].CE = trig_a ; "(1 term, 1 symbol) triggers.1.count[2].RESET = /triggers.1.q0 ; "(1 term, 1 symbol) triggers.1.count[2].XORL = triggers.1.count[2] ; "(1 term, 1 symbol) triggers.1.count[2].XORR = triggers.1.count[0]* triggers.1.count[1] ; "(1 term, 2 symbols) triggers.1.count[1].D = triggers.1.count[0]* /triggers.1.count[1] + /triggers.1.count[0]* triggers.1.count[1] ; "(2 terms, 2 symbols) triggers.1.count[1].CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.count[1].CE = trig_a ; "(1 term, 1 symbol) triggers.1.count[1].RESET = /triggers.1.q0 ; "(1 term, 1 symbol) triggers.1.count[0].D = /triggers.1.count[0] ; "(1 term, 1 symbol) triggers.1.count[0].CLK = nclk_4 ; "(1 term, 1 symbol) triggers.1.count[0].CE = trig_a ; "(1 term, 1 symbol) triggers.1.count[0].RESET = /triggers.1.q0 ; "(1 term, 1 symbol) error_and_a_reset.1.q1.CLK = nclk_4 ; "(1 term, 1 symbol) error_and_a_reset.1.q1.RESET = /noa_rst ; "(1 term, 1 symbol) error_and_a_reset.1.q1.D(~) = /merror*/verror ; "(1 term, 2 symbols) error_and_a_reset.1.q5.CLK = nclk_4 ; "(1 term, 1 symbol) error_and_a_reset.1.q5.RESET = /noa_rst ; "(1 term, 1 symbol) error_and_a_reset.1.q5.D(~) = /ext_error*next_error*/vt_error ; "(1 term, 3 symbols) error_and_a_reset.1.q3.D = /nenh_a_reset*/not_reset + va_reset ; "(2 terms, 3 symbols) error_and_a_reset.1.q3.CLK = nclk_4 ; "(1 term, 1 symbol) error_and_a_reset.1.q3.RESET = /error_and_a_reset.1.q34reset ; "(1 term, 1 symbol) error_and_a_reset.1.q34reset.EQN = /nenh_a_reset*/not_reset + noa_rst ; "(2 terms, 3 symbols) busys.1.busy_count[3].CLK = nclk_4 ; "(1 term, 1 symbol) busys.1.busy_count[3].CE = int_busy ; "(1 term, 1 symbol) busys.1.busy_count[3].RESET = busys.1.q2_reset ; "(1 term, 1 symbol) busys.1.busy_count[3].XORL = busys.1.busy_count[3] ; "(1 term, 1 symbol) busys.1.busy_count[3].XORR = busys.1.busy_count[0]* busys.1.busy_count[1]*busys.1.busy_count[2] ; "(1 term, 3 symbols) busys.1.busy_count[2].CLK = nclk_4 ; "(1 term, 1 symbol) busys.1.busy_count[2].CE = int_busy ; "(1 term, 1 symbol) busys.1.busy_count[2].RESET = busys.1.q2_reset ; "(1 term, 1 symbol) busys.1.busy_count[2].XORL = busys.1.busy_count[2] ; "(1 term, 1 symbol) busys.1.busy_count[2].XORR = busys.1.busy_count[0]* busys.1.busy_count[1] ; "(1 term, 2 symbols) busys.1.busy_count[1].D = busys.1.busy_count[0]* /busys.1.busy_count[1] + /busys.1.busy_count[0]* busys.1.busy_count[1] ; "(2 terms, 2 symbols) busys.1.busy_count[1].CLK = nclk_4 ; "(1 term, 1 symbol) busys.1.busy_count[1].CE = int_busy ; "(1 term, 1 symbol) busys.1.busy_count[1].RESET = busys.1.q2_reset ; "(1 term, 1 symbol) busys.1.busy_count[0].D = /busys.1.busy_count[0] ; "(1 term, 1 symbol) busys.1.busy_count[0].CLK = nclk_4 ; "(1 term, 1 symbol) busys.1.busy_count[0].CE = int_busy ; "(1 term, 1 symbol) busys.1.busy_count[0].RESET = busys.1.q2_reset ; "(1 term, 1 symbol) busys.1.q1_reset.EQN = /busys.1.level_to_pulse.1.pulse* entestbusy*noa_rst ; "(1 term, 3 symbols) busys.1.q2_reset.EQN = abortout + busys.1.busy_count[0]* busys.1.busy_count[1]*busys.1.busy_count[2]* busys.1.busy_count[3] + /noa_rst ; "(3 terms, 6 symbols) busys.1.level_to_pulse.1.pulse.D = 1 ; "(1 term, 0 symbols) busys.1.level_to_pulse.1.pulse.CLK = clrtestbusy ; "(1 term, 1 symbol) busys.1.level_to_pulse.1.pulse.RESET = busys.1.level_to_pulse.1.clr ; "(1 term, 1 symbol) busys.1.level_to_pulse.1.clr.EQN(~) = /busys.1.level_to_pulse.1.pulse* noa_rst ; "(1 term, 2 symbols) trigger_mpxers.1.q1.D = fltaccept ; "(1 term, 1 symbol) trigger_mpxers.1.q1.CLK = nclk_5 ; "(1 term, 1 symbol) trigger_mpxers.1.q1.RESET = /noa_rst ; "(1 term, 1 symbol) trigger_mpxers.1.q2.D = trigger_mpxers.1.q1 ; "(1 term, 1 symbol) trigger_mpxers.1.q2.CLK = nclk_5 ; "(1 term, 1 symbol) trigger_mpxers.1.q2.RESET = /noa_rst ; "(1 term, 1 symbol) trigger_mpxers.1.q3.D = trigger_mpxers.1.q2 ; "(1 term, 1 symbol) trigger_mpxers.1.q3.CLK = nclk_5 ; "(1 term, 1 symbol) trigger_mpxers.1.q3.RESET = /noa_rst ; "(1 term, 1 symbol) trigger_mpxers.1.q4.D = clocks.1.q2 ; "(1 term, 1 symbol) trigger_mpxers.1.q4.CLK = nclk_4 ; "(1 term, 1 symbol) trigger_mpxers.1.q4.RESET = /noa_rst ; "(1 term, 1 symbol) trigger_mpxers.1.q5.D = trigger_mpxers.1.q4 ; "(1 term, 1 symbol) trigger_mpxers.1.q5.CLK = nclk_4 ; "(1 term, 1 symbol) trigger_mpxers.1.q5.RESET = /noa_rst ; "(1 term, 1 symbol) test_pulse_and_delay.1.q1.D = 1 ; "(1 term, 0 symbols) test_pulse_and_delay.1.q1.CLK = testpulse ; "(1 term, 1 symbol) test_pulse_and_delay.1.q1.RESET = /test_pulse_and_delay.1.q1_reset ; "(1 term, 1 symbol) test_pulse_and_delay.1.q1_reset.EQN = noa_rst*/testcal_h ; "(1 term, 2 symbols) test_pulse_and_delay.1.testpulse_count[15].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[15].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[15].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[15].XORL = test_pulse_and_delay.1.testpulse_count[15] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[15].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[10]* test_pulse_and_delay.1.testpulse_count[11]* test_pulse_and_delay.1.testpulse_count[12]* test_pulse_and_delay.1.testpulse_count[13]* test_pulse_and_delay.1.testpulse_count[14]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6]* test_pulse_and_delay.1.testpulse_count[7]* test_pulse_and_delay.1.testpulse_count[8]* test_pulse_and_delay.1.testpulse_count[9] ; "(1 term, 15 symbols) test_pulse_and_delay.1.testpulse_count[14].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[14].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[14].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[14].XORL = test_pulse_and_delay.1.testpulse_count[14] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[14].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[10]* test_pulse_and_delay.1.testpulse_count[11]* test_pulse_and_delay.1.testpulse_count[12]* test_pulse_and_delay.1.testpulse_count[13]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6]* test_pulse_and_delay.1.testpulse_count[7]* test_pulse_and_delay.1.testpulse_count[8]* test_pulse_and_delay.1.testpulse_count[9] ; "(1 term, 14 symbols) test_pulse_and_delay.1.testpulse_count[13].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[13].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[13].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[13].XORL = test_pulse_and_delay.1.testpulse_count[13] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[13].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[10]* test_pulse_and_delay.1.testpulse_count[11]* test_pulse_and_delay.1.testpulse_count[12]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6]* test_pulse_and_delay.1.testpulse_count[7]* test_pulse_and_delay.1.testpulse_count[8]* test_pulse_and_delay.1.testpulse_count[9] ; "(1 term, 13 symbols) test_pulse_and_delay.1.testpulse_count[12].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[12].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[12].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[12].XORL = test_pulse_and_delay.1.testpulse_count[12] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[12].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[10]* test_pulse_and_delay.1.testpulse_count[11]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6]* test_pulse_and_delay.1.testpulse_count[7]* test_pulse_and_delay.1.testpulse_count[8]* test_pulse_and_delay.1.testpulse_count[9] ; "(1 term, 12 symbols) test_pulse_and_delay.1.testpulse_count[11].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[11].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[11].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[11].XORL = test_pulse_and_delay.1.testpulse_count[11] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[11].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[10]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6]* test_pulse_and_delay.1.testpulse_count[7]* test_pulse_and_delay.1.testpulse_count[8]* test_pulse_and_delay.1.testpulse_count[9] ; "(1 term, 11 symbols) test_pulse_and_delay.1.testpulse_count[10].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[10].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[10].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[10].XORL = test_pulse_and_delay.1.testpulse_count[10] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[10].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6]* test_pulse_and_delay.1.testpulse_count[7]* test_pulse_and_delay.1.testpulse_count[8]* test_pulse_and_delay.1.testpulse_count[9] ; "(1 term, 10 symbols) test_pulse_and_delay.1.testpulse_count[9].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[9].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[9].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[9].XORL = test_pulse_and_delay.1.testpulse_count[9] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[9].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6]* test_pulse_and_delay.1.testpulse_count[7]* test_pulse_and_delay.1.testpulse_count[8] ; "(1 term, 9 symbols) test_pulse_and_delay.1.testpulse_count[8].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[8].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[8].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[8].XORL = test_pulse_and_delay.1.testpulse_count[8] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[8].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6]* test_pulse_and_delay.1.testpulse_count[7] ; "(1 term, 8 symbols) test_pulse_and_delay.1.testpulse_count[7].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[7].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[7].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[7].XORL = test_pulse_and_delay.1.testpulse_count[7] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[7].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5]* test_pulse_and_delay.1.testpulse_count[6] ; "(1 term, 7 symbols) test_pulse_and_delay.1.testpulse_count[6].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[6].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[6].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[6].XORL = test_pulse_and_delay.1.testpulse_count[6] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[6].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4]* test_pulse_and_delay.1.testpulse_count[5] ; "(1 term, 6 symbols) test_pulse_and_delay.1.testpulse_count[5].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[5].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[5].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[5].XORL = test_pulse_and_delay.1.testpulse_count[5] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[5].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3]* test_pulse_and_delay.1.testpulse_count[4] ; "(1 term, 5 symbols) test_pulse_and_delay.1.testpulse_count[4].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[4].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[4].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[4].XORL = test_pulse_and_delay.1.testpulse_count[4] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[4].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2]* test_pulse_and_delay.1.testpulse_count[3] ; "(1 term, 4 symbols) test_pulse_and_delay.1.testpulse_count[3].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[3].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[3].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[3].XORL = test_pulse_and_delay.1.testpulse_count[3] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[3].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1]* test_pulse_and_delay.1.testpulse_count[2] ; "(1 term, 3 symbols) test_pulse_and_delay.1.testpulse_count[2].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[2].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[2].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[2].XORL = test_pulse_and_delay.1.testpulse_count[2] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[2].XORR = test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1] ; "(1 term, 2 symbols) test_pulse_and_delay.1.testpulse_count[1].D = test_pulse_and_delay.1.testpulse_count[0]* /test_pulse_and_delay.1.testpulse_count[1] + /test_pulse_and_delay.1.testpulse_count[0]* test_pulse_and_delay.1.testpulse_count[1] ; "(2 terms, 2 symbols) test_pulse_and_delay.1.testpulse_count[1].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[1].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[1].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[0].D = /test_pulse_and_delay.1.testpulse_count[0] ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[0].CLK = clk_6 ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[0].CE = testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.testpulse_count[0].RESET = /testpulse_busy ; "(1 term, 1 symbol) test_pulse_and_delay.1.equal_to-9.EQN = ctpdl[0]* /test_pulse_and_delay.1.testpulse_count[0] + /ctpdl[0]* test_pulse_and_delay.1.testpulse_count[0] + ctpdl[1]* /test_pulse_and_delay.1.testpulse_count[1] + /ctpdl[1]* test_pulse_and_delay.1.testpulse_count[1] + ctpdl[2]* /test_pulse_and_delay.1.testpulse_count[2] + /ctpdl[2]* test_pulse_and_delay.1.testpulse_count[2] + ctpdl[3]* /test_pulse_and_delay.1.testpulse_count[3] + /ctpdl[3]* test_pulse_and_delay.1.testpulse_count[3] + ctpdl[4]* /test_pulse_and_delay.1.testpulse_count[4] + /ctpdl[4]* test_pulse_and_delay.1.testpulse_count[4] + ctpdl[5]* /test_pulse_and_delay.1.testpulse_count[5] + /ctpdl[5]* test_pulse_and_delay.1.testpulse_count[5] + ctpdl[6]* /test_pulse_and_delay.1.testpulse_count[6] + /ctpdl[6]* test_pulse_and_delay.1.testpulse_count[6] + ctpdl[7]* /test_pulse_and_delay.1.testpulse_count[7] + /ctpdl[7]* test_pulse_and_delay.1.testpulse_count[7] ; "(16 terms, 16 symbols) test_pulse_and_delay.1.equal_to-16.EQN = ctpdl[10]* /test_pulse_and_delay.1.testpulse_count[10] + /ctpdl[10]* test_pulse_and_delay.1.testpulse_count[10] + ctpdl[11]* /test_pulse_and_delay.1.testpulse_count[11] + /ctpdl[11]* test_pulse_and_delay.1.testpulse_count[11] + ctpdl[12]* /test_pulse_and_delay.1.testpulse_count[12] + /ctpdl[12]* test_pulse_and_delay.1.testpulse_count[12] + ctpdl[13]* /test_pulse_and_delay.1.testpulse_count[13] + /ctpdl[13]* test_pulse_and_delay.1.testpulse_count[13] + ctpdl[14]* /test_pulse_and_delay.1.testpulse_count[14] + /ctpdl[14]* test_pulse_and_delay.1.testpulse_count[14] + ctpdl[15]* /test_pulse_and_delay.1.testpulse_count[15] + /ctpdl[15]* test_pulse_and_delay.1.testpulse_count[15] + ctpdl[8]* /test_pulse_and_delay.1.testpulse_count[8] + /ctpdl[8]* test_pulse_and_delay.1.testpulse_count[8] + ctpdl[9]* /test_pulse_and_delay.1.testpulse_count[9] + /ctpdl[9]* test_pulse_and_delay.1.testpulse_count[9] ; "(16 terms, 16 symbols) clocks.1.q1.D = testenout ; "(1 term, 1 symbol) clocks.1.q1.CLK = clk_1 ; "(1 term, 1 symbol) clocks.1.q1.RESET = /noa_rst ; "(1 term, 1 symbol) clocks.1.q2.D = acceptout ; "(1 term, 1 symbol) clocks.1.q2.CLK = clk_1 ; "(1 term, 1 symbol) clocks.1.q2.RESET = /noa_rst ; "(1 term, 1 symbol) clocks.1.q3.D = a_accept ; "(1 term, 1 symbol) clocks.1.q3.CLK = nclk_4 ; "(1 term, 1 symbol) clocks.1.q3.RESET = /noa_rst ; "(1 term, 1 symbol) clocks.1.q4.D = trig_a ; "(1 term, 1 symbol) clocks.1.q4.CLK = nclk_4 ; "(1 term, 1 symbol) clocks.1.q4.RESET = /noa_rst ; "(1 term, 1 symbol) clocks.1.q5.D = abortout ; "(1 term, 1 symbol) clocks.1.q5.CLK = nclk_4 ; "(1 term, 1 symbol) clocks.1.q5.RESET = /noa_rst ; "(1 term, 1 symbol) mode_init.1.q4_reset.EQN = /bcn0gflt*/local_bcn0_s24* /neninitreset*noa_rst + /bcn0gflt*/neninitreset*noa_rst* /wrcontr1 + /neninitreset*noa_rst*/h_reset ; "(3 terms, 6 symbols) select_lines.1.da_counter_clk.EQN = nclk_4*a_accept + da[1]*da[0]*a_accept ; "(2 terms, 4 symbols) select_lines.1.da_counter_reset.EQN = noa_rst*a_accept ; "(1 term, 2 symbols) last_abort.1.q3.D = lasttrig_abort ; "(1 term, 1 symbol) last_abort.1.q3.CLK = a_accept ; "(1 term, 1 symbol) last_abort.1.q3.RESET = /last_abort.1.q_reset ; "(1 term, 1 symbol) last_abort.1.q_reset.EQN = /last_abort.1.q3*noa_rst ; "(1 term, 2 symbols) PLDocument: Y:\clock\zeus\master\pld4\pld4.doc SOLUTIONS Tue Feb 29 15:25:56 2000 PARTITIONING CRITERIA : WEIGHT PRICE 10 ; TEMPLATE = M4-32/32 OR M4-256/128; PARTITIONING SOLUTIONS : ==> Solution 1: MV512_184 FUSEMAP FILES FOR SOLUTION 1: Device 1 (MV512_184) : Y:\clock\zeus\master\pld4\pld4.j1 PLDocument: Y:\clock\zeus\master\pld4\pld4.doc PINOUT DIAGRAMS Tue Feb 29 15:25:56 2000 Device 1 - MV512_184 -- Pinout for QFP package +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 1 |Jtag | | | 51 |Vcc | | | 2 |Biput | ctpdl[0] | | 52 |Biput | rosys[0] | | 3 |Biput | ctpdl[1] | | 53 |Biput | rosys[1] | | 4 |Biput | ctpdl[2] | | 54 |Biput | fltaccept | | 5 |Biput | ctpdl[3] | | 55 |Biput | acceptout | | 6 |Biput | ctpdl[4] | | 56 |Biput | s_trig | | 7 |Biput | ctpdl[5] | | 57 |Biput | initialise | | 8 |Biput | ctpdl[6] | | 58 |Biput | t_errorout | | 9 |Biput | ctpdl[7] | | 59 |Biput | ntrig_a | | 10 |Vcc | | | 60 |Jtag | | | 11 |GND | | | 61 |GND | | | 12 |Biput | ctpdl[8] | | 62 |Vcc | | | 13 |Biput | ctpdl[9] | | 63 |Biput | a_abort | | 14 |Biput | ctpdl[10] | | 64 |Biput | acceptclk[1] | | 15 |Biput | ctpdl[11] | | 65 |Biput | acceptclk[2] | | 16 |Biput | ctpdl[12] | | 66 |Biput | acceptclk[3] | | 17 |Biput | ctpdl[13] | | 67 |Biput | a_accept | | 18 |Biput | ctpdl[14] | | 68 |Biput | entestbusy | | 19 |Biput | ctpdl[15] | | 69 |Biput | testenclk1 | | 20 |GND | | | 70 |Biput | a_reset | | 21 |Biput | da[0] | | 71 |GND | | | 22 |Biput | da[1] | | 72 |Vcc | | | 23 |Biput | testcal_h | | 73 |Biput | | | 24 |Biput | lasttrig_abort | | 74 |Biput | | | 25 |Biput | | | 75 |Biput | clrtestbusy | | 26 |Biput | neninitreset | | 76 |Biput | na_reset | | 27 |Biput | abortout | | 77 |Biput | testbusy | | 28 |Biput | | | 78 |Biput | wrcontr1 | | 29 |In/CLK| nclk_4 | | 79 |Biput | testenout | | 30 |Vcc | | | 80 |Biput | clk_1 | | 31 |GND | | | 81 |GND | | | 32 |In/CLK| clk_6 | | 82 |Biput | gflt_mode | | 33 |Biput | | | 83 |Biput | local_mode | | 34 |Biput | ext_error | | 84 |Biput | | | 35 |Biput | envar_trig | | 85 |Biput | | | 36 |Biput | ext_trig | | 86 |Biput | testpulse | | 37 |Biput | vt_error | | 87 |Biput | | | 38 |Biput | trig_h | | 88 |Vcc | | | 39 |Biput | ncal_busy | | 89 |GND | | | 40 |Biput | | | 90 |GND | | | 41 |GND | | | 91 |GND | | | 42 |Biput | nbusy_1 | | 92 |GND | | | 43 |Biput | busyout | | 93 |Vcc | | | 44 |Biput | int_busy | | 94 |Biput | va_reset | | 45 |Biput | trig_a | | 95 |Biput | bcn0gflt | | 46 |Biput | busy_1 | | 96 |Biput | ninit_reset | | 47 |Biput | noa_rst | | 97 |Biput | | | 48 |Biput | trig_in | | 98 |Biput | nenh_a_reset | | 49 |Biput | vtrigger | | 99 |Biput | vh_reset | | 50 |GND | | | 100 |GND | | +-------+------+----------------------+ +-------+------+----------------------+ Device 1 - MV512_184 -- Pinout for QFP package (continued) +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 101 |Biput | lbusy[1] | | 151 |GND | | | 102 |Biput | lbusy[2] | | 152 |In/CLK| | | 103 |Biput | lbusy[3] | | 153 |Biput | lf_errormask[1] | | 104 |Biput | lbusy[4] | | 154 |Biput | lf_errormask[2] | | 105 |Biput | lbusy[5] | | 155 |Biput | lf_errormask[3] | | 106 |Biput | init_reset | | 156 |Biput | lf_errormask[4] | | 107 |Biput | verror | | 157 |Biput | lf_errormask[5] | | 108 |Biput | nenoa_rst | | 158 |Biput | mbusy | | 109 |Vcc | | | 159 |Biput | | | 110 |GND | | | 160 |Biput | mf_error | | 111 |Biput | lbusymask[1] | | 161 |GND | | | 112 |Biput | lbusymask[2] | | 162 |Biput | seltt[0] | | 113 |Biput | lbusymask[3] | | 163 |Biput | seltt[1] | | 114 |Biput | lbusymask[4] | | 164 |Biput | seltt[2] | | 115 |Biput | lbusymask[5] | | 165 |Biput | ttyp[0] | | 116 |Biput | not_reset | | 166 |Biput | ttyp[1] | | 117 |Biput | errorout | | 167 |Biput | ttyp[2] | | 118 |Biput | h_reset | | 168 |Biput | | | 119 |Vcc | | | 169 |Biput | merror | | 120 |GND | | | 170 |GND | | | 121 |Jtag | | | 171 |Vcc | | | 122 |Biput | lerror[1] | | 172 |Biput | vbusy | | 123 |Biput | lerror[2] | | 173 |Biput | f_errorout | | 124 |Biput | lerror[3] | | 174 |Biput | cal_busy | | 125 |Biput | lerror[4] | | 175 |Biput | vcalibrate | | 126 |Biput | lerror[5] | | 176 |Biput | fcstp | | 127 |Biput | noa_reset | | 177 |Biput | cal_trig | | 128 |Biput | s_rst | | 178 |Biput | cal_h | | 129 |Biput | vmoa_reset | | 179 |Biput | vf_error | | 130 |Vcc | | | 180 |Jtag | | | 131 |GND | | | 181 |GND | | | 132 |Biput | lerrormask[1] | | 182 |Vcc | | | 133 |Biput | lerrormask[2] | | 183 |Biput | | | 134 |Biput | lerrormask[3] | | 184 |Biput | ntestpulse_busy | | 135 |Biput | lerrormask[4] | | 185 |Biput | | | 136 |Biput | lerrormask[5] | | 186 |Biput | | | 137 |Biput | | | 187 |Biput | | | 138 |Biput | | | 188 |Biput | testpulse_busy | | 139 |Biput | oa_reset | | 189 |Biput | | | 140 |GND | | | 190 |Biput | | | 141 |Biput | lf_error[1] | | 191 |GND | | | 142 |Biput | lf_error[2] | | 192 |Vcc | | | 143 |Biput | lf_error[3] | | 193 |Biput | nerrorout | | 144 |Biput | lf_error[4] | | 194 |Biput | next_error | | 145 |Biput | lf_error[5] | | 195 |Biput | | | 146 |Biput | | | 196 |Biput | | | 147 |Biput | | | 197 |Biput | | | 148 |Biput | | | 198 |Biput | | | 149 |In/CLK| nclk_5 | | 199 |Biput | | | 150 |Vcc | | | 200 |Biput | | +-------+------+----------------------+ +-------+------+----------------------+ Device 1 - MV512_184 -- Pinout for QFP package (continued) +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 201 |GND | | | 221 |Biput | s14[0] | | 202 |Biput | cctdl[0] | | 222 |Biput | s14[1] | | 203 |Biput | cctdl[1] | | 223 |Biput | s14[2] | | 204 |Biput | cctdl[2] | | 224 |Biput | s14[3] | | 205 |Biput | cctdl[3] | | 225 |Biput | local_bcn0_s24 | | 206 |Biput | cctdl[4] | | 226 |Biput | ttypout_s24[0] | | 207 |Biput | cctdl[5] | | 227 |Biput | ttypout_s24[1] | | 208 |Vcc | | | 228 |Biput | ttypout_s24[2] | | 209 |GND | | | 229 |Vcc | | | 210 |GND | | | 230 |GND | | | 211 |GND | | | 231 |Biput | s34[0] | | 212 |GND | | | 232 |Biput | m_busy_s34 | | 213 |Vcc | | | 233 |Biput | rosysout_s34[0] | | 214 |Biput | | | 234 |Biput | rosysout_s34[1] | | 215 |Biput | | | 235 |Biput | | | 216 |Biput | | | 236 |Biput | | | 217 |Biput | | | 237 |Biput | | | 218 |Biput | | | 238 |Biput | | | 219 |Biput | | | 239 |Vcc | | | 220 |GND | | | 240 |GND | | +-------+------+----------------------+ +-------+------+----------------------+ DEVICE SELECTION: Device Man Fam Pack Temp ICC TPD Fmax Price User ==> M5-512/184-7HC AMD CMOS QFP COM 999.9ma 9.5ns 105.0MHz $ 0.00 0 0 PLDocument: Y:\clock\zeus\master\pld4\pld4.doc WIRELIST Tue Feb 29 15:25:56 2000 +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | envar_trig | MV512_184_1 | 35 | | s_trig | MV512_184_1 | 56 | | ext_trig | MV512_184_1 | 36 | | vtrigger | MV512_184_1 | 49 | | nclk_4 | MV512_184_1 | 29 | | nclk_5 | MV512_184_1 | 149 | | clk_6 | MV512_184_1 | 32 | | noa_rst | MV512_184_1 | 47 | | s_rst | MV512_184_1 | 128 | | vmoa_reset | MV512_184_1 | 129 | | vcalibrate | MV512_184_1 | 175 | | cctdl[5] | MV512_184_1 | 207 | | cctdl[4] | MV512_184_1 | 206 | | cctdl[3] | MV512_184_1 | 205 | | cctdl[2] | MV512_184_1 | 204 | | cctdl[1] | MV512_184_1 | 203 | | cctdl[0] | MV512_184_1 | 202 | | vf_error | MV512_184_1 | 179 | | vbusy | MV512_184_1 | 172 | | verror | MV512_184_1 | 107 | | va_reset | MV512_184_1 | 94 | | nenh_a_reset | MV512_184_1 | 98 | | vt_error | MV512_184_1 | 37 | | ext_error | MV512_184_1 | 34 | | next_error | MV512_184_1 | 194 | | vh_reset | MV512_184_1 | 99 | | nenoa_rst | MV512_184_1 | 108 | | acceptout | MV512_184_1 | 55 | | rosysout_s34[1] | MV512_184_1 | 234 | | rosysout_s34[0] | MV512_184_1 | 233 | | entestbusy | MV512_184_1 | 68 | | abortout | MV512_184_1 | 27 | | clrtestbusy | MV512_184_1 | 75 | | lbusy[5] | MV512_184_1 | 105 | | lbusy[4] | MV512_184_1 | 104 | | lbusy[3] | MV512_184_1 | 103 | | lbusy[2] | MV512_184_1 | 102 | | lbusy[1] | MV512_184_1 | 101 | | lbusymask[5] | MV512_184_1 | 115 | | lbusymask[4] | MV512_184_1 | 114 | | lbusymask[3] | MV512_184_1 | 113 | | lbusymask[2] | MV512_184_1 | 112 | | lbusymask[1] | MV512_184_1 | 111 | | lerror[5] | MV512_184_1 | 126 | | lerror[4] | MV512_184_1 | 125 | | lerror[3] | MV512_184_1 | 124 | | lerror[2] | MV512_184_1 | 123 | | lerror[1] | MV512_184_1 | 122 | | lerrormask[5] | MV512_184_1 | 136 | | lerrormask[4] | MV512_184_1 | 135 | | lerrormask[3] | MV512_184_1 | 134 | +------------------+-------------------+-------+ +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | lerrormask[2] | MV512_184_1 | 133 | | lerrormask[1] | MV512_184_1 | 132 | | lf_error[5] | MV512_184_1 | 145 | | lf_error[4] | MV512_184_1 | 144 | | lf_error[3] | MV512_184_1 | 143 | | lf_error[2] | MV512_184_1 | 142 | | lf_error[1] | MV512_184_1 | 141 | | lf_errormask[5] | MV512_184_1 | 157 | | lf_errormask[4] | MV512_184_1 | 156 | | lf_errormask[3] | MV512_184_1 | 155 | | lf_errormask[2] | MV512_184_1 | 154 | | lf_errormask[1] | MV512_184_1 | 153 | | ttypout_s24[2] | MV512_184_1 | 228 | | ttypout_s24[1] | MV512_184_1 | 227 | | ttypout_s24[0] | MV512_184_1 | 226 | | seltt[2] | MV512_184_1 | 164 | | seltt[1] | MV512_184_1 | 163 | | seltt[0] | MV512_184_1 | 162 | | ctpdl[15] | MV512_184_1 | 19 | | ctpdl[14] | MV512_184_1 | 18 | | ctpdl[13] | MV512_184_1 | 17 | | ctpdl[12] | MV512_184_1 | 16 | | ctpdl[11] | MV512_184_1 | 15 | | ctpdl[10] | MV512_184_1 | 14 | | ctpdl[9] | MV512_184_1 | 13 | | ctpdl[8] | MV512_184_1 | 12 | | ctpdl[7] | MV512_184_1 | 9 | | ctpdl[6] | MV512_184_1 | 8 | | ctpdl[5] | MV512_184_1 | 7 | | ctpdl[4] | MV512_184_1 | 6 | | ctpdl[3] | MV512_184_1 | 5 | | ctpdl[2] | MV512_184_1 | 4 | | ctpdl[1] | MV512_184_1 | 3 | | ctpdl[0] | MV512_184_1 | 2 | | testenout | MV512_184_1 | 79 | | clk_1 | MV512_184_1 | 80 | | wrcontr1 | MV512_184_1 | 78 | | bcn0gflt | MV512_184_1 | 95 | | neninitreset | MV512_184_1 | 26 | | local_bcn0_s24 | MV512_184_1 | 225 | | ttyp[2] | MV512_184_1 | 167 | | ttyp[1] | MV512_184_1 | 166 | | ttyp[0] | MV512_184_1 | 165 | | rosys[1] | MV512_184_1 | 53 | | rosys[0] | MV512_184_1 | 52 | | trig_a | MV512_184_1 | 45 | | trig_h | MV512_184_1 | 38 | | ntrig_a | MV512_184_1 | 59 | | cal_h | MV512_184_1 | 178 | | oa_reset | MV512_184_1 | 139 | | noa_reset | MV512_184_1 | 127 | +------------------+-------------------+-------+ +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | cal_trig | MV512_184_1 | 177 | | cal_busy | MV512_184_1 | 174 | | ncal_busy | MV512_184_1 | 39 | | f_errorout | MV512_184_1 | 173 | | busy_1 | MV512_184_1 | 46 | | nbusy_1 | MV512_184_1 | 42 | | errorout | MV512_184_1 | 117 | | t_errorout | MV512_184_1 | 58 | | nerrorout | MV512_184_1 | 193 | | h_reset | MV512_184_1 | 118 | | not_reset | MV512_184_1 | 116 | | busyout | MV512_184_1 | 43 | | int_busy | MV512_184_1 | 44 | | a_reset | MV512_184_1 | 70 | | na_reset | MV512_184_1 | 76 | | testbusy | MV512_184_1 | 77 | | testpulse | MV512_184_1 | 86 | | testcal_h | MV512_184_1 | 23 | | a_accept | MV512_184_1 | 67 | | trig_in | MV512_184_1 | 48 | | initialise | MV512_184_1 | 57 | | fltaccept | MV512_184_1 | 54 | | fcstp | MV512_184_1 | 176 | | mbusy | MV512_184_1 | 158 | | merror | MV512_184_1 | 169 | | mf_error | MV512_184_1 | 160 | | testpulse_busy | MV512_184_1 | 188 | | ntestpulse_busy | MV512_184_1 | 184 | | testenclk1 | MV512_184_1 | 69 | | acceptclk[3] | MV512_184_1 | 66 | | acceptclk[2] | MV512_184_1 | 65 | | acceptclk[1] | MV512_184_1 | 64 | | a_abort | MV512_184_1 | 63 | | local_mode | MV512_184_1 | 83 | | gflt_mode | MV512_184_1 | 82 | | init_reset | MV512_184_1 | 106 | | ninit_reset | MV512_184_1 | 96 | | da[1] | MV512_184_1 | 22 | | da[0] | MV512_184_1 | 21 | | lasttrig_abort | MV512_184_1 | 24 | | m_busy_s34 | MV512_184_1 | 232 | | s14[3] | MV512_184_1 | 224 | | s14[2] | MV512_184_1 | 223 | | s14[1] | MV512_184_1 | 222 | | s14[0] | MV512_184_1 | 221 | | s34[0] | MV512_184_1 | 231 | +------------------+-------------------+-------+