"=================================================================================================== #TITLE 'ZEUS MVD C&C MASTER, PLD3, REGISTERS 06 thru 14'; #ENGINEER 'Martin Postranecky / Dominic A Hayes'; #COMPANY 'University College London'; #COMMENT ''; "=================================================================================================== "26/jul/99 wrcontr1 now LOW_TRUE o/p. "11/jan/00 leb2 clocking now /leb2. " empty register o/p's set to 0. "25feb00 rosysout from pld2 routed via this chip to pld4. "28feb00 moved "--------------------------------------------------------------------------------------------------- LOW_TRUE INPUT noa_rst; INPUT slaveclk1; "--------------------------------------------------------------------------------------- "VME derived signals "------------------- LOW_TRUE INPUT bwriteb; LOW_TRUE INPUT breadb; LOW_TRUE INPUT reg06, reg08, reg0A, reg0C, reg0E, reg10, reg12, reg14; LOW_TRUE INPUT leb2; "databus BIPUT db[15..0] ENABLED_BY dboe; NODE dboe; "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "SPARE I/O "--------- INPUT s13[4]; "spare outputs. INPUT s23[2]; "spare outputs. was 4 INPUT s34[1]; "spare outputs. was 4 INPUT empty_i[9]; "input to empty register slots. OUTPUT empty_o[3]; "output from empty register slots. "--------------------------------------------------------------------------------------- "ROSYSOUT via this chip "---------------------- INPUT rosysout_s23[1..0]; "rosysout from pld2. OUTPUT rosysout_s34[1..0]; "rosysout to pld4. "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register06, ** MASTER COMMAND ** (VME READ/WRITE) " ---------------------- NODE register06[15..0] CLOCKED_BY /leb2 RESET_BY noa_rst DEFAULT_TO LAST_VALUE; LOW_TRUE OUTPUT wrcontr1; "wrcontr1 now OUTPUT LOW_TRUE OUTPUT vmoa_reset, vbusy, vf_error, vt_error, verror, envar_trig, vtrigger, vcalibrate, vh_reset, va_reset, entestbusy, clrtestbusy; wrcontr1 = register06[0]; vmoa_reset = register06[1]; empty_o[0] = 0; "register06[2]; vbusy = register06[3]; vf_error = register06[4]; vt_error = register06[5]; verror = register06[6]; envar_trig = register06[7]; vtrigger = register06[8]; vcalibrate = register06[9]; vh_reset = register06[10]; va_reset = register06[11]; empty_o[1] = 0; "register06[12]; empty_o[2] = 0; "register06[13]; entestbusy = register06[14]; clrtestbusy = register06[15]; "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register08 [not clocked] ** MASTER STATE ** (MASTER WRITE / VME READ) " -------------------- INPUT local_mode, gflt_mode, aclk_on, hclk_on, errorout, trig_in, fcstp, h_reset, a_reset, lasttrig_abort, a_accept, cal_busy, testbusy; INPUT m_busy_s34; NODE register08[15..0]; register08 = [testbusy, cal_busy, a_accept, lasttrig_abort, a_reset, h_reset, fcstp, trig_in, 0, " empty_i[9], errorout, hclk_on, aclk_on, m_busy_s34, 0, " empty_i[7], gflt_mode, local_mode]; "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register0A ** TEST STATE ** (MASTER WRITE / VME READ) " ------------------ INPUT aclk_fault, hclk_fault, pll_fault, a_abort; "plus NODE register0A[15..0]; "trig_in, fcstp, a_accept, h_reset, a_reset. NODE r0A[15..0]; NODE reset_0A; " SELF-CLOCKING SIGNALS "----------------------- r0A[15] = reset_0A AND (empty_i[6] OR r0A[15]); r0A[14] = reset_0A AND (empty_i[5] OR r0A[14]); r0A[13] = reset_0A AND (a_accept OR r0A[13]); r0A[12] = reset_0A AND (a_abort OR r0A[12]); r0A[11] = reset_0A AND (a_reset OR r0A[11]); r0A[10] = reset_0A AND (h_reset OR r0A[10]); r0A[9] = reset_0A AND (fcstp OR r0A[9] ); r0A[8] = reset_0A AND (trig_in OR r0A[8] ); r0A[7] = reset_0A AND (empty_i[4] OR r0A[7] ); r0A[6] = reset_0A AND (pll_fault OR r0A[6] ); r0A[5] = reset_0A AND (aclk_fault OR r0A[5] ); r0A[4] = reset_0A AND (hclk_fault OR r0A[4] ); r0A[3] = reset_0A AND (empty_i[3] OR r0A[3] ); r0A[2] = reset_0A AND (empty_i[2] OR r0A[2] ); r0A[1] = reset_0A AND (empty_i[1] OR r0A[1] ); r0A[0] = reset_0A AND (empty_i[0] OR r0A[0] ); register0A = [ 0, 0, " r0A[15], r0A[14], " empty_i[6], empty_i[5], r0A[13], r0A[12], r0A[11], r0A[10], r0A[9], r0A[8], " a_accept a_abort a_reset h_reset fcstp trig_in 0, " r0A[7], " empty_i[4], r0A[6], r0A[5], r0A[4], " pll_fault aclk_fault hclk_fault 0, 0, 0, 0 ]; " r0A[3], r0A[2], r0A[1], r0A[0] ]; " empty_i[3], empty_i[2], empty_i[1], empty_i[0] reset_0A = /(noa_rst OR (reg0A AND bwriteb)); "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register0C ** SLAVES STATE ** (SLAVE WRITE / VME READ) " ------------------- (with MASTER O/Ps) INPUT busy[5..1], error[5..1], f_error[5..1]; NODE register0C[15..0] CLOCKED_BY slaveclk1 RESET_BY noa_rst DEFAULT_TO LAST_VALUE; OUTPUT lbusy[5..1], lerror[5..1], lf_error[5..1]; register0C[4..0] = busy[5..1] ; " register0C[9..5] = error[5..1] ; " INPUT from SLAVEs. register0C[14..10] = f_error[5..1] ; " register0C[15] = 0 ; lbusy[5..1] = register0C[4..0] ; lerror[5..1] = register0C[9..5] ; "OUTPUT to MASTER. lf_error[5..1] = register0C[14..10]; "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register0E ** SLAVE MASK ** (VME READ/WRITE) " ------------------ NODE register0E[15..0] CLOCKED_BY /leb2 RESET_BY noa_rst DEFAULT_TO LAST_VALUE; OUTPUT lbusymask[5..1]; OUTPUT lerrormask[5..1]; OUTPUT lf_errormask[5..1]; lbusymask[5..1] = register0E[4..0]; lerrormask[5..1] = register0E[9..5]; lf_errormask[5..1] = register0E[14..10]; "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register10 ** CALIB TRIGGER DELAY ** (VME READ/WRITE) " --------------------------- NODE register10[15..0] "bit 6 now spare (as well as 7) CLOCKED_BY /leb2 RESET_BY noa_rst DEFAULT_TO LAST_VALUE; OUTPUT cctdl[5..0], fctdl[7..0]; fctdl[7..0] = register10[15..8]; cctdl[5..0] = register10[5..0]; "reduced from 7 o/ps to 6, 21/5/99. " register10[7..6] set to whatever VME db[7..6] are when clocked. "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register12 ** HCLOCK DELAY ** (VME READ/WRITE) " ------------------- NODE register12[15..0] CLOCKED_BY /leb2 RESET_BY noa_rst DEFAULT_TO LAST_VALUE; OUTPUT hcdl[7..0]; OUTPUT s1dl[7..0]; "spare outputs hcdl[7..0] = register12[7..0]; s1dl[7..0] = register12[15..8]; "empty bits " register12[15..8] set to whatever VME db[15..8] are when clocked. "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register14 ** TEST PULSE DELAY ** (VME READ/WRITE) " ----------------------- NODE register14[15..0] CLOCKED_BY /leb2 RESET_BY noa_rst DEFAULT_TO LAST_VALUE; OUTPUT ctpdl[15..0]; ctpdl[15..0] = register14[15..0]; "--------------------------------------------------------------------------------------- "================================================================================================== " VME databus db assignment "--------------------------- dboe = breadb AND (reg06 OR reg08 OR reg0A OR reg0C OR reg0E OR reg10 OR reg12 OR reg14); "OE IF (bwriteb) THEN "VME WRITES to registers. IF (reg06) THEN register06 = db; ELSIF (reg0E) THEN register0E = db; ELSIF (reg10) THEN register10 = db; ELSIF (reg12) THEN register12 = db; ELSIF (reg14) THEN register14 = db; END IF; ELSIF (breadb) THEN "VME READS the registers. IF (reg06) THEN db = register06; ELSIF (reg08) THEN db = register08; ELSIF (reg0A) THEN db = register0A; ELSIF (reg0C) THEN db = register0C; ELSIF (reg0E) THEN db = register0E; ELSIF (reg10) THEN db = register10; ELSIF (reg12) THEN db = register12; ELSIF (reg14) THEN db = register14; END IF; END IF; "------------------------------------------------------------------------ " ROSYSOUT "---------- rosysout_s34[1..0] = rosysout_s23[1..0]; "ROUTED ONLY "==================================================================================================