PLDocument:  Y:\clock\zeus\master\pld3\pld3.doc
                  TITLE PAGE  Mon Feb 28 15:13:14 2000



   A MACHXL6.2.1.11 - (c) Copyright MINC Incorporated 1987-1998


==============================================================================

     TITLE    : ZEUS MVD C&C MASTER, PLD3, REGISTERS 06 thru 14
     FILE     : Y:\clock\zeus\master\pld3\pld3.mpf
     DATE     : Thu Jun 04 02:36:00 1970
     ENGINEER : Martin Postranecky / Dominic A Hayes
     COMPANY  : University College London

==============================================================================


     MODULES  :

        Document Generator     	  3.70
        File Handler           	  6.2
        Language Compiler      	  3.83
        Architectural Optimizer	  3.110
        Device Lib Scan        	  3.2
        Device Library         	  3.17
        Device Partition       	  3.21
        Device Fusemap         	  3.4



     SWITCH VALUES :

        (Value in parenthesis represents batch mode switch value)

        PLCOMP PRODUCT TERM LIMIT : 128
        PLOPT  PRODUCT TERM LIMIT : 128
        PLOPT REDUCTION  :   Espresso (1)
        NODE GENERATION  :   Procedure Instantiation
                             Arithmetic and Relational Operators (1)


PLDocument:  Y:\clock\zeus\master\pld3\pld3.doc
                  EQUATIONS  Mon Feb 28 15:13:14 2000


EQUATIONS FOR SYSTEM

INPUT SIGNALS (64) :

       LOW_TRUE   noa_rst
       slaveclk1
       LOW_TRUE   bwriteb
       LOW_TRUE   breadb
       LOW_TRUE   reg06
       LOW_TRUE   reg08
       LOW_TRUE   reg0A
       LOW_TRUE   reg0C
       LOW_TRUE   reg0E
       LOW_TRUE   reg10
       LOW_TRUE   reg12
       LOW_TRUE   reg14
       LOW_TRUE   leb2
       s13[3..0]
       s23[1..0]
       s34[0]
       empty_i[8..0]
       rosysout_s23[1..0]
       local_mode
       gflt_mode
       aclk_on
       hclk_on
       errorout
       trig_in
       fcstp
       h_reset
       a_reset
       lasttrig_abort
       a_accept
       cal_busy
       testbusy
       m_busy_s34
       aclk_fault
       hclk_fault
       pll_fault
       a_abort
       busy[5..1]
       error[5..1]
       f_error[5..1]

OUTPUT SIGNALS (110) :

       db[15..0]
       empty_o[2..0]
       rosysout_s34[1..0]
       clrtestbusy
       entestbusy
       va_reset
       vh_reset
       vcalibrate
       vtrigger
       envar_trig
       verror
       vt_error
       vf_error
       vbusy
       vmoa_reset
       LOW_TRUE   wrcontr1
       lf_error[5..1]
       lerror[5..1]
       lbusy[5..1]
       lf_errormask[5..1]
       lerrormask[5..1]
       lbusymask[5..1]
       fctdl[7..0]
       cctdl[5..0]
       s1dl[7..0]
       hcdl[7..0]
       ctpdl[15..0]

PHYSICAL NODE SIGNALS (17) :

       dboe
       register06[13..12]
       register06[2]
       r0A[13..8]
       r0A[6..4]
       register0C[15]
       register0E[15]
       register10[7..6]


REDUCED EQUATIONS:


db[15].EQN = reg06*clrtestbusy
                 + /reg06*reg08*testbusy
                 + /reg06*/reg08*/reg0A*reg0C*
                     register0C[15]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     register0E[15]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*fctdl[7]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*s1dl[7]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[15] ;  "(7 terms, 14 symbols)
db[15].OE = dboe ;  "(1 term, 1 symbol)

db[14].EQN = cal_busy*/reg06*reg08
                 + reg06*entestbusy
                 + /reg06*/reg08*/reg0A*reg0C*
                     lf_error[5]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lf_errormask[5]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*fctdl[6]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*s1dl[6]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[14] ;  "(7 terms, 14 symbols)
db[14].OE = dboe ;  "(1 term, 1 symbol)

db[13].EQN = a_accept*/reg06*reg08
                 + r0A[13]*/reg06*/reg08*reg0A
                 + reg06*register06[13]
                 + /reg06*/reg08*/reg0A*reg0C*
                     lf_error[4]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lf_errormask[4]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*fctdl[5]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*s1dl[5]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[13] ;  "(8 terms, 15 symbols)
db[13].OE = dboe ;  "(1 term, 1 symbol)

db[12].EQN = lasttrig_abort*/reg06*reg08
                 + r0A[12]*/reg06*/reg08*reg0A
                 + reg06*register06[12]
                 + /reg06*/reg08*/reg0A*reg0C*
                     lf_error[3]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lf_errormask[3]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*fctdl[4]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*s1dl[4]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[12] ;  "(8 terms, 15 symbols)
db[12].OE = dboe ;  "(1 term, 1 symbol)

db[11].EQN = a_reset*/reg06*reg08
                 + r0A[11]*/reg06*/reg08*reg0A
                 + reg06*va_reset
                 + /reg06*/reg08*/reg0A*reg0C*
                     lf_error[2]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lf_errormask[2]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*fctdl[3]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*s1dl[3]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[11] ;  "(8 terms, 15 symbols)
db[11].OE = dboe ;  "(1 term, 1 symbol)

db[10].EQN = h_reset*/reg06*reg08
                 + r0A[10]*/reg06*/reg08*reg0A
                 + reg06*vh_reset
                 + /reg06*/reg08*/reg0A*reg0C*
                     lf_error[1]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lf_errormask[1]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*fctdl[2]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*s1dl[2]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[10] ;  "(8 terms, 15 symbols)
db[10].OE = dboe ;  "(1 term, 1 symbol)

db[9].EQN = fcstp*/reg06*reg08
                 + r0A[9]*/reg06*/reg08*reg0A
                 + reg06*vcalibrate
                 + /reg06*/reg08*/reg0A*reg0C*
                     lerror[5]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lerrormask[5]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*fctdl[1]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*s1dl[1]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[9] ;  "(8 terms, 15 symbols)
db[9].OE = dboe ;  "(1 term, 1 symbol)

db[8].EQN = r0A[8]*/reg06*/reg08*reg0A
                 + reg06*vtrigger
                 + /reg06*reg08*trig_in
                 + /reg06*/reg08*/reg0A*reg0C*
                     lerror[4]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lerrormask[4]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*fctdl[0]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*s1dl[0]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[8] ;  "(8 terms, 15 symbols)
db[8].OE = dboe ;  "(1 term, 1 symbol)

db[7].EQN = reg06*envar_trig
                 + /reg06*/reg08*/reg0A*reg0C*
                     lerror[3]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lerrormask[3]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*register10[7]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*hcdl[7]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[7] ;  "(6 terms, 13 symbols)
db[7].OE = dboe ;  "(1 term, 1 symbol)

db[6].EQN = errorout*/reg06*reg08
                 + r0A[6]*/reg06*/reg08*reg0A
                 + reg06*verror
                 + /reg06*/reg08*/reg0A*reg0C*
                     lerror[2]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lerrormask[2]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*register10[6]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*hcdl[6]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[6] ;  "(8 terms, 15 symbols)
db[6].OE = dboe ;  "(1 term, 1 symbol)

db[5].EQN = hclk_on*/reg06*reg08
                 + r0A[5]*/reg06*/reg08*reg0A
                 + reg06*vt_error
                 + /reg06*/reg08*/reg0A*reg0C*
                     lerror[1]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lerrormask[1]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*cctdl[5]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*hcdl[5]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[5] ;  "(8 terms, 15 symbols)
db[5].OE = dboe ;  "(1 term, 1 symbol)

db[4].EQN = aclk_on*/reg06*reg08
                 + r0A[4]*/reg06*/reg08*reg0A
                 + reg06*vf_error
                 + /reg06*/reg08*/reg0A*reg0C*lbusy[5]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lbusymask[5]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*cctdl[4]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*hcdl[4]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[4] ;  "(8 terms, 15 symbols)
db[4].OE = dboe ;  "(1 term, 1 symbol)

db[3].EQN = m_busy_s34*/reg06*reg08
                 + reg06*vbusy
                 + /reg06*/reg08*/reg0A*reg0C*lbusy[4]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lbusymask[4]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*cctdl[3]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*hcdl[3]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[3] ;  "(7 terms, 14 symbols)
db[3].OE = dboe ;  "(1 term, 1 symbol)

db[2].EQN = reg06*register06[2]
                 + /reg06*/reg08*/reg0A*reg0C*lbusy[3]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lbusymask[3]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*cctdl[2]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*hcdl[2]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[2] ;  "(6 terms, 13 symbols)
db[2].OE = dboe ;  "(1 term, 1 symbol)

db[1].EQN = gflt_mode*/reg06*reg08
                 + reg06*vmoa_reset
                 + /reg06*/reg08*/reg0A*reg0C*lbusy[2]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lbusymask[2]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*cctdl[1]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*hcdl[1]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[1] ;  "(7 terms, 14 symbols)
db[1].OE = dboe ;  "(1 term, 1 symbol)

db[0].EQN = local_mode*/reg06*reg08
                 + reg06*wrcontr1
                 + /reg06*/reg08*/reg0A*reg0C*lbusy[1]
                 + /reg06*/reg08*/reg0A*/reg0C*reg0E*
                     lbusymask[1]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     reg10*cctdl[0]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*reg12*hcdl[0]
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*ctpdl[0] ;  "(7 terms, 14 symbols)
db[0].OE = dboe ;  "(1 term, 1 symbol)

dboe.EQN(~) = /breadb
                 + /reg06*/reg08*/reg0A*/reg0C*/reg0E*
                     /reg10*/reg12*/reg14 ;  "(2 terms, 9 symbols)

empty_o[2].EQN = 0 ;  "(1 term, 0 symbols)

empty_o[1].EQN = 0 ;  "(1 term, 0 symbols)

empty_o[0].EQN = 0 ;  "(1 term, 0 symbols)

rosysout_s34[1].EQN = rosysout_s23[1] ;  "(1 term, 1 symbol)

rosysout_s34[0].EQN = rosysout_s23[0] ;  "(1 term, 1 symbol)

clrtestbusy.D = bwriteb*db[15]*reg06
                 + /bwriteb*clrtestbusy
                 + /reg06*clrtestbusy ;  "(3 terms, 4 symbols)
clrtestbusy.CLK = /leb2 ;  "(1 term, 1 symbol)
clrtestbusy.RESET = noa_rst ;  "(1 term, 1 symbol)

entestbusy.D = bwriteb*db[14]*reg06
                 + /bwriteb*entestbusy
                 + /reg06*entestbusy ;  "(3 terms, 4 symbols)
entestbusy.CLK = /leb2 ;  "(1 term, 1 symbol)
entestbusy.RESET = noa_rst ;  "(1 term, 1 symbol)

register06[13].D = bwriteb*db[13]*reg06
                 + /bwriteb*register06[13]
                 + /reg06*register06[13] ;  "(3 terms, 4 symbols)
register06[13].CLK = /leb2 ;  "(1 term, 1 symbol)
register06[13].RESET = noa_rst ;  "(1 term, 1 symbol)

register06[12].D = bwriteb*db[12]*reg06
                 + /bwriteb*register06[12]
                 + /reg06*register06[12] ;  "(3 terms, 4 symbols)
register06[12].CLK = /leb2 ;  "(1 term, 1 symbol)
register06[12].RESET = noa_rst ;  "(1 term, 1 symbol)

va_reset.D = bwriteb*db[11]*reg06
                 + /bwriteb*va_reset
                 + /reg06*va_reset ;  "(3 terms, 4 symbols)
va_reset.CLK = /leb2 ;  "(1 term, 1 symbol)
va_reset.RESET = noa_rst ;  "(1 term, 1 symbol)

vh_reset.D = bwriteb*db[10]*reg06
                 + /bwriteb*vh_reset
                 + /reg06*vh_reset ;  "(3 terms, 4 symbols)
vh_reset.CLK = /leb2 ;  "(1 term, 1 symbol)
vh_reset.RESET = noa_rst ;  "(1 term, 1 symbol)

vcalibrate.D = bwriteb*db[9]*reg06
                 + /bwriteb*vcalibrate
                 + /reg06*vcalibrate ;  "(3 terms, 4 symbols)
vcalibrate.CLK = /leb2 ;  "(1 term, 1 symbol)
vcalibrate.RESET = noa_rst ;  "(1 term, 1 symbol)

vtrigger.D = bwriteb*db[8]*reg06
                 + /bwriteb*vtrigger
                 + /reg06*vtrigger ;  "(3 terms, 4 symbols)
vtrigger.CLK = /leb2 ;  "(1 term, 1 symbol)
vtrigger.RESET = noa_rst ;  "(1 term, 1 symbol)

envar_trig.D = bwriteb*db[7]*reg06
                 + /bwriteb*envar_trig
                 + /reg06*envar_trig ;  "(3 terms, 4 symbols)
envar_trig.CLK = /leb2 ;  "(1 term, 1 symbol)
envar_trig.RESET = noa_rst ;  "(1 term, 1 symbol)

verror.D = bwriteb*db[6]*reg06
                 + /bwriteb*verror
                 + /reg06*verror ;  "(3 terms, 4 symbols)
verror.CLK = /leb2 ;  "(1 term, 1 symbol)
verror.RESET = noa_rst ;  "(1 term, 1 symbol)

vt_error.D = bwriteb*db[5]*reg06
                 + /bwriteb*vt_error
                 + /reg06*vt_error ;  "(3 terms, 4 symbols)
vt_error.CLK = /leb2 ;  "(1 term, 1 symbol)
vt_error.RESET = noa_rst ;  "(1 term, 1 symbol)

vf_error.D = bwriteb*db[4]*reg06
                 + /bwriteb*vf_error
                 + /reg06*vf_error ;  "(3 terms, 4 symbols)
vf_error.CLK = /leb2 ;  "(1 term, 1 symbol)
vf_error.RESET = noa_rst ;  "(1 term, 1 symbol)

vbusy.D = bwriteb*db[3]*reg06
                 + /bwriteb*vbusy
                 + /reg06*vbusy ;  "(3 terms, 4 symbols)
vbusy.CLK = /leb2 ;  "(1 term, 1 symbol)
vbusy.RESET = noa_rst ;  "(1 term, 1 symbol)

register06[2].D = bwriteb*db[2]*reg06
                 + /bwriteb*register06[2]
                 + /reg06*register06[2] ;  "(3 terms, 4 symbols)
register06[2].CLK = /leb2 ;  "(1 term, 1 symbol)
register06[2].RESET = noa_rst ;  "(1 term, 1 symbol)

vmoa_reset.D = bwriteb*db[1]*reg06
                 + /bwriteb*vmoa_reset
                 + /reg06*vmoa_reset ;  "(3 terms, 4 symbols)
vmoa_reset.CLK = /leb2 ;  "(1 term, 1 symbol)
vmoa_reset.RESET = noa_rst ;  "(1 term, 1 symbol)

wrcontr1.D = bwriteb*db[0]*reg06
                 + /bwriteb*wrcontr1
                 + /reg06*wrcontr1 ;  "(3 terms, 4 symbols)
wrcontr1.CLK = /leb2 ;  "(1 term, 1 symbol)
wrcontr1.RESET = noa_rst ;  "(1 term, 1 symbol)

r0A[13].EQN(~) = /a_accept*/r0A[13]
                 + bwriteb*reg0A
                 + noa_rst ;  "(3 terms, 5 symbols)

r0A[12].EQN(~) = /a_abort*/r0A[12]
                 + bwriteb*reg0A
                 + noa_rst ;  "(3 terms, 5 symbols)

r0A[11].EQN(~) = /a_reset*/r0A[11]
                 + bwriteb*reg0A
                 + noa_rst ;  "(3 terms, 5 symbols)

r0A[10].EQN(~) = bwriteb*reg0A
                 + /h_reset*/r0A[10]
                 + noa_rst ;  "(3 terms, 5 symbols)

r0A[9].EQN(~) = bwriteb*reg0A
                 + /fcstp*/r0A[9]
                 + noa_rst ;  "(3 terms, 5 symbols)

r0A[8].EQN(~) = bwriteb*reg0A
                 + noa_rst
                 + /r0A[8]*/trig_in ;  "(3 terms, 5 symbols)

r0A[6].EQN(~) = bwriteb*reg0A
                 + noa_rst
                 + /pll_fault*/r0A[6] ;  "(3 terms, 5 symbols)

r0A[5].EQN(~) = /aclk_fault*/r0A[5]
                 + bwriteb*reg0A
                 + noa_rst ;  "(3 terms, 5 symbols)

r0A[4].EQN(~) = bwriteb*reg0A
                 + /hclk_fault*/r0A[4]
                 + noa_rst ;  "(3 terms, 5 symbols)

register0C[15].D = 0 ;  "(1 term, 0 symbols)
register0C[15].CLK = slaveclk1 ;  "(1 term, 1 symbol)
register0C[15].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_error[5].D = f_error[5] ;  "(1 term, 1 symbol)
lf_error[5].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lf_error[5].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_error[4].D = f_error[4] ;  "(1 term, 1 symbol)
lf_error[4].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lf_error[4].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_error[3].D = f_error[3] ;  "(1 term, 1 symbol)
lf_error[3].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lf_error[3].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_error[2].D = f_error[2] ;  "(1 term, 1 symbol)
lf_error[2].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lf_error[2].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_error[1].D = f_error[1] ;  "(1 term, 1 symbol)
lf_error[1].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lf_error[1].RESET = noa_rst ;  "(1 term, 1 symbol)

lerror[5].D = error[5] ;  "(1 term, 1 symbol)
lerror[5].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lerror[5].RESET = noa_rst ;  "(1 term, 1 symbol)

lerror[4].D = error[4] ;  "(1 term, 1 symbol)
lerror[4].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lerror[4].RESET = noa_rst ;  "(1 term, 1 symbol)

lerror[3].D = error[3] ;  "(1 term, 1 symbol)
lerror[3].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lerror[3].RESET = noa_rst ;  "(1 term, 1 symbol)

lerror[2].D = error[2] ;  "(1 term, 1 symbol)
lerror[2].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lerror[2].RESET = noa_rst ;  "(1 term, 1 symbol)

lerror[1].D = error[1] ;  "(1 term, 1 symbol)
lerror[1].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lerror[1].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusy[5].D = busy[5] ;  "(1 term, 1 symbol)
lbusy[5].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lbusy[5].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusy[4].D = busy[4] ;  "(1 term, 1 symbol)
lbusy[4].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lbusy[4].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusy[3].D = busy[3] ;  "(1 term, 1 symbol)
lbusy[3].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lbusy[3].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusy[2].D = busy[2] ;  "(1 term, 1 symbol)
lbusy[2].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lbusy[2].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusy[1].D = busy[1] ;  "(1 term, 1 symbol)
lbusy[1].CLK = slaveclk1 ;  "(1 term, 1 symbol)
lbusy[1].RESET = noa_rst ;  "(1 term, 1 symbol)

register0E[15].T = bwriteb*db[15]*/reg06*reg0E*
                     /register0E[15]
                 + bwriteb*/db[15]*/reg06*reg0E*
                     register0E[15] ;  "(2 terms, 5 symbols)
register0E[15].CLK = /leb2 ;  "(1 term, 1 symbol)
register0E[15].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_errormask[5].T = bwriteb*db[14]*/lf_errormask[5]*/reg06
                     *reg0E
                 + bwriteb*/db[14]*lf_errormask[5]*
                     /reg06*reg0E ;  "(2 terms, 5 symbols)
lf_errormask[5].CLK = /leb2 ;  "(1 term, 1 symbol)
lf_errormask[5].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_errormask[4].T = bwriteb*db[13]*/lf_errormask[4]*/reg06
                     *reg0E
                 + bwriteb*/db[13]*lf_errormask[4]*
                     /reg06*reg0E ;  "(2 terms, 5 symbols)
lf_errormask[4].CLK = /leb2 ;  "(1 term, 1 symbol)
lf_errormask[4].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_errormask[3].T = bwriteb*db[12]*/lf_errormask[3]*/reg06
                     *reg0E
                 + bwriteb*/db[12]*lf_errormask[3]*
                     /reg06*reg0E ;  "(2 terms, 5 symbols)
lf_errormask[3].CLK = /leb2 ;  "(1 term, 1 symbol)
lf_errormask[3].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_errormask[2].T = bwriteb*db[11]*/lf_errormask[2]*/reg06
                     *reg0E
                 + bwriteb*/db[11]*lf_errormask[2]*
                     /reg06*reg0E ;  "(2 terms, 5 symbols)
lf_errormask[2].CLK = /leb2 ;  "(1 term, 1 symbol)
lf_errormask[2].RESET = noa_rst ;  "(1 term, 1 symbol)

lf_errormask[1].T = bwriteb*db[10]*/lf_errormask[1]*/reg06
                     *reg0E
                 + bwriteb*/db[10]*lf_errormask[1]*
                     /reg06*reg0E ;  "(2 terms, 5 symbols)
lf_errormask[1].CLK = /leb2 ;  "(1 term, 1 symbol)
lf_errormask[1].RESET = noa_rst ;  "(1 term, 1 symbol)

lerrormask[5].T = bwriteb*db[9]*/lerrormask[5]*/reg06*
                     reg0E
                 + bwriteb*/db[9]*lerrormask[5]*/reg06
                     *reg0E ;  "(2 terms, 5 symbols)
lerrormask[5].CLK = /leb2 ;  "(1 term, 1 symbol)
lerrormask[5].RESET = noa_rst ;  "(1 term, 1 symbol)

lerrormask[4].T = bwriteb*db[8]*/lerrormask[4]*/reg06*
                     reg0E
                 + bwriteb*/db[8]*lerrormask[4]*/reg06
                     *reg0E ;  "(2 terms, 5 symbols)
lerrormask[4].CLK = /leb2 ;  "(1 term, 1 symbol)
lerrormask[4].RESET = noa_rst ;  "(1 term, 1 symbol)

lerrormask[3].T = bwriteb*db[7]*/lerrormask[3]*/reg06*
                     reg0E
                 + bwriteb*/db[7]*lerrormask[3]*/reg06
                     *reg0E ;  "(2 terms, 5 symbols)
lerrormask[3].CLK = /leb2 ;  "(1 term, 1 symbol)
lerrormask[3].RESET = noa_rst ;  "(1 term, 1 symbol)

lerrormask[2].T = bwriteb*db[6]*/lerrormask[2]*/reg06*
                     reg0E
                 + bwriteb*/db[6]*lerrormask[2]*/reg06
                     *reg0E ;  "(2 terms, 5 symbols)
lerrormask[2].CLK = /leb2 ;  "(1 term, 1 symbol)
lerrormask[2].RESET = noa_rst ;  "(1 term, 1 symbol)

lerrormask[1].T = bwriteb*db[5]*/lerrormask[1]*/reg06*
                     reg0E
                 + bwriteb*/db[5]*lerrormask[1]*/reg06
                     *reg0E ;  "(2 terms, 5 symbols)
lerrormask[1].CLK = /leb2 ;  "(1 term, 1 symbol)
lerrormask[1].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusymask[5].T = bwriteb*db[4]*/lbusymask[5]*/reg06*
                     reg0E
                 + bwriteb*/db[4]*lbusymask[5]*/reg06*
                     reg0E ;  "(2 terms, 5 symbols)
lbusymask[5].CLK = /leb2 ;  "(1 term, 1 symbol)
lbusymask[5].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusymask[4].T = bwriteb*db[3]*/lbusymask[4]*/reg06*
                     reg0E
                 + bwriteb*/db[3]*lbusymask[4]*/reg06*
                     reg0E ;  "(2 terms, 5 symbols)
lbusymask[4].CLK = /leb2 ;  "(1 term, 1 symbol)
lbusymask[4].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusymask[3].T = bwriteb*db[2]*/lbusymask[3]*/reg06*
                     reg0E
                 + bwriteb*/db[2]*lbusymask[3]*/reg06*
                     reg0E ;  "(2 terms, 5 symbols)
lbusymask[3].CLK = /leb2 ;  "(1 term, 1 symbol)
lbusymask[3].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusymask[2].T = bwriteb*db[1]*/lbusymask[2]*/reg06*
                     reg0E
                 + bwriteb*/db[1]*lbusymask[2]*/reg06*
                     reg0E ;  "(2 terms, 5 symbols)
lbusymask[2].CLK = /leb2 ;  "(1 term, 1 symbol)
lbusymask[2].RESET = noa_rst ;  "(1 term, 1 symbol)

lbusymask[1].T = bwriteb*db[0]*/lbusymask[1]*/reg06*
                     reg0E
                 + bwriteb*/db[0]*lbusymask[1]*/reg06*
                     reg0E ;  "(2 terms, 5 symbols)
lbusymask[1].CLK = /leb2 ;  "(1 term, 1 symbol)
lbusymask[1].RESET = noa_rst ;  "(1 term, 1 symbol)

fctdl[7].T = bwriteb*db[15]*/fctdl[7]*/reg06*/reg0E
                     *reg10
                 + bwriteb*/db[15]*fctdl[7]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
fctdl[7].CLK = /leb2 ;  "(1 term, 1 symbol)
fctdl[7].RESET = noa_rst ;  "(1 term, 1 symbol)

fctdl[6].T = bwriteb*db[14]*/fctdl[6]*/reg06*/reg0E
                     *reg10
                 + bwriteb*/db[14]*fctdl[6]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
fctdl[6].CLK = /leb2 ;  "(1 term, 1 symbol)
fctdl[6].RESET = noa_rst ;  "(1 term, 1 symbol)

fctdl[5].T = bwriteb*db[13]*/fctdl[5]*/reg06*/reg0E
                     *reg10
                 + bwriteb*/db[13]*fctdl[5]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
fctdl[5].CLK = /leb2 ;  "(1 term, 1 symbol)
fctdl[5].RESET = noa_rst ;  "(1 term, 1 symbol)

fctdl[4].T = bwriteb*db[12]*/fctdl[4]*/reg06*/reg0E
                     *reg10
                 + bwriteb*/db[12]*fctdl[4]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
fctdl[4].CLK = /leb2 ;  "(1 term, 1 symbol)
fctdl[4].RESET = noa_rst ;  "(1 term, 1 symbol)

fctdl[3].T = bwriteb*db[11]*/fctdl[3]*/reg06*/reg0E
                     *reg10
                 + bwriteb*/db[11]*fctdl[3]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
fctdl[3].CLK = /leb2 ;  "(1 term, 1 symbol)
fctdl[3].RESET = noa_rst ;  "(1 term, 1 symbol)

fctdl[2].T = bwriteb*db[10]*/fctdl[2]*/reg06*/reg0E
                     *reg10
                 + bwriteb*/db[10]*fctdl[2]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
fctdl[2].CLK = /leb2 ;  "(1 term, 1 symbol)
fctdl[2].RESET = noa_rst ;  "(1 term, 1 symbol)

fctdl[1].T = bwriteb*db[9]*/fctdl[1]*/reg06*/reg0E*
                     reg10
                 + bwriteb*/db[9]*fctdl[1]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
fctdl[1].CLK = /leb2 ;  "(1 term, 1 symbol)
fctdl[1].RESET = noa_rst ;  "(1 term, 1 symbol)

fctdl[0].T = bwriteb*db[8]*/fctdl[0]*/reg06*/reg0E*
                     reg10
                 + bwriteb*/db[8]*fctdl[0]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
fctdl[0].CLK = /leb2 ;  "(1 term, 1 symbol)
fctdl[0].RESET = noa_rst ;  "(1 term, 1 symbol)

register10[7].T = bwriteb*db[7]*/reg06*/reg0E*reg10*
                     /register10[7]
                 + bwriteb*/db[7]*/reg06*/reg0E*reg10*
                     register10[7] ;  "(2 terms, 6 symbols)
register10[7].CLK = /leb2 ;  "(1 term, 1 symbol)
register10[7].RESET = noa_rst ;  "(1 term, 1 symbol)

register10[6].T = bwriteb*db[6]*/reg06*/reg0E*reg10*
                     /register10[6]
                 + bwriteb*/db[6]*/reg06*/reg0E*reg10*
                     register10[6] ;  "(2 terms, 6 symbols)
register10[6].CLK = /leb2 ;  "(1 term, 1 symbol)
register10[6].RESET = noa_rst ;  "(1 term, 1 symbol)

cctdl[5].T = bwriteb*cctdl[5]*/db[5]*/reg06*/reg0E*
                     reg10
                 + bwriteb*/cctdl[5]*db[5]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
cctdl[5].CLK = /leb2 ;  "(1 term, 1 symbol)
cctdl[5].RESET = noa_rst ;  "(1 term, 1 symbol)

cctdl[4].T = bwriteb*cctdl[4]*/db[4]*/reg06*/reg0E*
                     reg10
                 + bwriteb*/cctdl[4]*db[4]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
cctdl[4].CLK = /leb2 ;  "(1 term, 1 symbol)
cctdl[4].RESET = noa_rst ;  "(1 term, 1 symbol)

cctdl[3].T = bwriteb*cctdl[3]*/db[3]*/reg06*/reg0E*
                     reg10
                 + bwriteb*/cctdl[3]*db[3]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
cctdl[3].CLK = /leb2 ;  "(1 term, 1 symbol)
cctdl[3].RESET = noa_rst ;  "(1 term, 1 symbol)

cctdl[2].T = bwriteb*cctdl[2]*/db[2]*/reg06*/reg0E*
                     reg10
                 + bwriteb*/cctdl[2]*db[2]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
cctdl[2].CLK = /leb2 ;  "(1 term, 1 symbol)
cctdl[2].RESET = noa_rst ;  "(1 term, 1 symbol)

cctdl[1].T = bwriteb*cctdl[1]*/db[1]*/reg06*/reg0E*
                     reg10
                 + bwriteb*/cctdl[1]*db[1]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
cctdl[1].CLK = /leb2 ;  "(1 term, 1 symbol)
cctdl[1].RESET = noa_rst ;  "(1 term, 1 symbol)

cctdl[0].T = bwriteb*cctdl[0]*/db[0]*/reg06*/reg0E*
                     reg10
                 + bwriteb*/cctdl[0]*db[0]*/reg06*
                     /reg0E*reg10 ;  "(2 terms, 6 symbols)
cctdl[0].CLK = /leb2 ;  "(1 term, 1 symbol)
cctdl[0].RESET = noa_rst ;  "(1 term, 1 symbol)

s1dl[7].T = bwriteb*db[15]*/reg06*/reg0E*/reg10*
                     reg12*/s1dl[7]
                 + bwriteb*/db[15]*/reg06*/reg0E*
                     /reg10*reg12*s1dl[7] ;  "(2 terms, 7 symbols)
s1dl[7].CLK = /leb2 ;  "(1 term, 1 symbol)
s1dl[7].RESET = noa_rst ;  "(1 term, 1 symbol)

s1dl[6].T = bwriteb*db[14]*/reg06*/reg0E*/reg10*
                     reg12*/s1dl[6]
                 + bwriteb*/db[14]*/reg06*/reg0E*
                     /reg10*reg12*s1dl[6] ;  "(2 terms, 7 symbols)
s1dl[6].CLK = /leb2 ;  "(1 term, 1 symbol)
s1dl[6].RESET = noa_rst ;  "(1 term, 1 symbol)

s1dl[5].T = bwriteb*db[13]*/reg06*/reg0E*/reg10*
                     reg12*/s1dl[5]
                 + bwriteb*/db[13]*/reg06*/reg0E*
                     /reg10*reg12*s1dl[5] ;  "(2 terms, 7 symbols)
s1dl[5].CLK = /leb2 ;  "(1 term, 1 symbol)
s1dl[5].RESET = noa_rst ;  "(1 term, 1 symbol)

s1dl[4].T = bwriteb*db[12]*/reg06*/reg0E*/reg10*
                     reg12*/s1dl[4]
                 + bwriteb*/db[12]*/reg06*/reg0E*
                     /reg10*reg12*s1dl[4] ;  "(2 terms, 7 symbols)
s1dl[4].CLK = /leb2 ;  "(1 term, 1 symbol)
s1dl[4].RESET = noa_rst ;  "(1 term, 1 symbol)

s1dl[3].T = bwriteb*db[11]*/reg06*/reg0E*/reg10*
                     reg12*/s1dl[3]
                 + bwriteb*/db[11]*/reg06*/reg0E*
                     /reg10*reg12*s1dl[3] ;  "(2 terms, 7 symbols)
s1dl[3].CLK = /leb2 ;  "(1 term, 1 symbol)
s1dl[3].RESET = noa_rst ;  "(1 term, 1 symbol)

s1dl[2].T = bwriteb*db[10]*/reg06*/reg0E*/reg10*
                     reg12*/s1dl[2]
                 + bwriteb*/db[10]*/reg06*/reg0E*
                     /reg10*reg12*s1dl[2] ;  "(2 terms, 7 symbols)
s1dl[2].CLK = /leb2 ;  "(1 term, 1 symbol)
s1dl[2].RESET = noa_rst ;  "(1 term, 1 symbol)

s1dl[1].T = bwriteb*db[9]*/reg06*/reg0E*/reg10*
                     reg12*/s1dl[1]
                 + bwriteb*/db[9]*/reg06*/reg0E*/reg10
                     *reg12*s1dl[1] ;  "(2 terms, 7 symbols)
s1dl[1].CLK = /leb2 ;  "(1 term, 1 symbol)
s1dl[1].RESET = noa_rst ;  "(1 term, 1 symbol)

s1dl[0].T = bwriteb*db[8]*/reg06*/reg0E*/reg10*
                     reg12*/s1dl[0]
                 + bwriteb*/db[8]*/reg06*/reg0E*/reg10
                     *reg12*s1dl[0] ;  "(2 terms, 7 symbols)
s1dl[0].CLK = /leb2 ;  "(1 term, 1 symbol)
s1dl[0].RESET = noa_rst ;  "(1 term, 1 symbol)

hcdl[7].T = bwriteb*db[7]*/hcdl[7]*/reg06*/reg0E*
                     /reg10*reg12
                 + bwriteb*/db[7]*hcdl[7]*/reg06*
                     /reg0E*/reg10*reg12 ;  "(2 terms, 7 symbols)
hcdl[7].CLK = /leb2 ;  "(1 term, 1 symbol)
hcdl[7].RESET = noa_rst ;  "(1 term, 1 symbol)

hcdl[6].T = bwriteb*db[6]*/hcdl[6]*/reg06*/reg0E*
                     /reg10*reg12
                 + bwriteb*/db[6]*hcdl[6]*/reg06*
                     /reg0E*/reg10*reg12 ;  "(2 terms, 7 symbols)
hcdl[6].CLK = /leb2 ;  "(1 term, 1 symbol)
hcdl[6].RESET = noa_rst ;  "(1 term, 1 symbol)

hcdl[5].T = bwriteb*db[5]*/hcdl[5]*/reg06*/reg0E*
                     /reg10*reg12
                 + bwriteb*/db[5]*hcdl[5]*/reg06*
                     /reg0E*/reg10*reg12 ;  "(2 terms, 7 symbols)
hcdl[5].CLK = /leb2 ;  "(1 term, 1 symbol)
hcdl[5].RESET = noa_rst ;  "(1 term, 1 symbol)

hcdl[4].T = bwriteb*db[4]*/hcdl[4]*/reg06*/reg0E*
                     /reg10*reg12
                 + bwriteb*/db[4]*hcdl[4]*/reg06*
                     /reg0E*/reg10*reg12 ;  "(2 terms, 7 symbols)
hcdl[4].CLK = /leb2 ;  "(1 term, 1 symbol)
hcdl[4].RESET = noa_rst ;  "(1 term, 1 symbol)

hcdl[3].T = bwriteb*db[3]*/hcdl[3]*/reg06*/reg0E*
                     /reg10*reg12
                 + bwriteb*/db[3]*hcdl[3]*/reg06*
                     /reg0E*/reg10*reg12 ;  "(2 terms, 7 symbols)
hcdl[3].CLK = /leb2 ;  "(1 term, 1 symbol)
hcdl[3].RESET = noa_rst ;  "(1 term, 1 symbol)

hcdl[2].T = bwriteb*db[2]*/hcdl[2]*/reg06*/reg0E*
                     /reg10*reg12
                 + bwriteb*/db[2]*hcdl[2]*/reg06*
                     /reg0E*/reg10*reg12 ;  "(2 terms, 7 symbols)
hcdl[2].CLK = /leb2 ;  "(1 term, 1 symbol)
hcdl[2].RESET = noa_rst ;  "(1 term, 1 symbol)

hcdl[1].T = bwriteb*db[1]*/hcdl[1]*/reg06*/reg0E*
                     /reg10*reg12
                 + bwriteb*/db[1]*hcdl[1]*/reg06*
                     /reg0E*/reg10*reg12 ;  "(2 terms, 7 symbols)
hcdl[1].CLK = /leb2 ;  "(1 term, 1 symbol)
hcdl[1].RESET = noa_rst ;  "(1 term, 1 symbol)

hcdl[0].T = bwriteb*db[0]*/hcdl[0]*/reg06*/reg0E*
                     /reg10*reg12
                 + bwriteb*/db[0]*hcdl[0]*/reg06*
                     /reg0E*/reg10*reg12 ;  "(2 terms, 7 symbols)
hcdl[0].CLK = /leb2 ;  "(1 term, 1 symbol)
hcdl[0].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[15].T = bwriteb*ctpdl[15]*/db[15]*/reg06*
                     /reg0E*/reg10*/reg12*reg14
                 + bwriteb*/ctpdl[15]*db[15]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[15].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[15].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[14].T = bwriteb*ctpdl[14]*/db[14]*/reg06*
                     /reg0E*/reg10*/reg12*reg14
                 + bwriteb*/ctpdl[14]*db[14]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[14].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[14].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[13].T = bwriteb*ctpdl[13]*/db[13]*/reg06*
                     /reg0E*/reg10*/reg12*reg14
                 + bwriteb*/ctpdl[13]*db[13]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[13].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[13].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[12].T = bwriteb*ctpdl[12]*/db[12]*/reg06*
                     /reg0E*/reg10*/reg12*reg14
                 + bwriteb*/ctpdl[12]*db[12]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[12].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[12].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[11].T = bwriteb*ctpdl[11]*/db[11]*/reg06*
                     /reg0E*/reg10*/reg12*reg14
                 + bwriteb*/ctpdl[11]*db[11]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[11].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[11].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[10].T = bwriteb*ctpdl[10]*/db[10]*/reg06*
                     /reg0E*/reg10*/reg12*reg14
                 + bwriteb*/ctpdl[10]*db[10]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[10].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[10].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[9].T = bwriteb*ctpdl[9]*/db[9]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[9]*db[9]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[9].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[9].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[8].T = bwriteb*ctpdl[8]*/db[8]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[8]*db[8]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[8].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[8].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[7].T = bwriteb*ctpdl[7]*/db[7]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[7]*db[7]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[7].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[7].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[6].T = bwriteb*ctpdl[6]*/db[6]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[6]*db[6]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[6].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[6].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[5].T = bwriteb*ctpdl[5]*/db[5]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[5]*db[5]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[5].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[5].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[4].T = bwriteb*ctpdl[4]*/db[4]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[4]*db[4]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[4].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[4].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[3].T = bwriteb*ctpdl[3]*/db[3]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[3]*db[3]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[3].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[3].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[2].T = bwriteb*ctpdl[2]*/db[2]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[2]*db[2]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[2].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[2].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[1].T = bwriteb*ctpdl[1]*/db[1]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[1]*db[1]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[1].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[1].RESET = noa_rst ;  "(1 term, 1 symbol)

ctpdl[0].T = bwriteb*ctpdl[0]*/db[0]*/reg06*/reg0E*
                     /reg10*/reg12*reg14
                 + bwriteb*/ctpdl[0]*db[0]*/reg06*
                     /reg0E*/reg10*/reg12*reg14 ;  "(2 terms, 8 symbols)
ctpdl[0].CLK = /leb2 ;  "(1 term, 1 symbol)
ctpdl[0].RESET = noa_rst ;  "(1 term, 1 symbol)

PLDocument:  Y:\clock\zeus\master\pld3\pld3.doc
                  SOLUTIONS  Mon Feb 28 15:13:14 2000


 PARTITIONING CRITERIA : 


 

WEIGHT PRICE 10 ;

 

TEMPLATE =  M4-32/32 OR M4-256/128;






PARTITIONING SOLUTIONS : 

==> Solution  1: MV512_184 



FUSEMAP FILES FOR SOLUTION 1: 

  Device 1 (MV512_184) : Y:\clock\zeus\master\pld3\pld3.j1

PLDocument:  Y:\clock\zeus\master\pld3\pld3.doc
                  PINOUT DIAGRAMS  Mon Feb 28 15:13:14 2000


             Device  1 - MV512_184 -- Pinout for QFP package

+-------+------+----------------------+ +-------+------+----------------------+ 
|  Pin  | Type |        Signal        | |  Pin  | Type |        Signal        |
+-------+------+----------------------+ +-------+------+----------------------+ 
|    1  |Jtag  |                      | |   51  |Vcc   |                      |
|    2  |Biput |  busy[1]             | |   52  |Biput |  reg06               |
|    3  |Biput |  busy[2]             | |   53  |Biput |  reg08               |
|    4  |Biput |  busy[3]             | |   54  |Biput |  reg0A               |
|    5  |Biput |  busy[4]             | |   55  |Biput |  reg0C               |
|    6  |Biput |  busy[5]             | |   56  |Biput |  reg0E               |
|    7  |Biput |  db[8]               | |   57  |Biput |  reg10               |
|    8  |Biput |  envar_trig          | |   58  |Biput |  reg12               |
|    9  |Biput |  db[7]               | |   59  |Biput |  reg14               |
|   10  |Vcc   |                      | |   60  |Jtag  |                      |
|   11  |GND   |                      | |   61  |GND   |                      |
|   12  |Biput |  error[1]            | |   62  |Vcc   |                      |
|   13  |Biput |  error[2]            | |   63  |Biput |  cctdl[0]            |
|   14  |Biput |  error[3]            | |   64  |Biput |  cctdl[1]            |
|   15  |Biput |  error[4]            | |   65  |Biput |  cctdl[2]            |
|   16  |Biput |  error[5]            | |   66  |Biput |  cctdl[3]            |
|   17  |Biput |  lerrormask[3]       | |   67  |Biput |  cctdl[4]            |
|   18  |Biput |  lerrormask[4]       | |   68  |Biput |  cctdl[5]            |
|   19  |Biput |  db[6]               | |   69  |Biput |  db[0]               |
|   20  |GND   |                      | |   70  |Biput |  lasttrig_abort      |
|   21  |Biput |  f_error[1]          | |   71  |GND   |                      |
|   22  |Biput |  f_error[2]          | |   72  |Vcc   |                      |
|   23  |Biput |  f_error[3]          | |   73  |Biput |  breadb              |
|   24  |Biput |  f_error[4]          | |   74  |Biput |  s13[3]              |
|   25  |Biput |  f_error[5]          | |   75  |Biput |  noa_rst             |
|   26  |Biput |  vtrigger            | |   76  |Biput |  lbusymask[3]        |
|   27  |Biput |  verror              | |   77  |Biput |  lbusymask[1]        |
|   28  |Biput |  lerrormask[2]       | |   78  |Biput |  empty_o[0]          |
|   29  |In/CLK|  leb2                | |   79  |Biput |  bwriteb             |
|   30  |Vcc   |                      | |   80  |Biput |  wrcontr1            |
|   31  |GND   |                      | |   81  |GND   |                      |
|   32  |In/CLK|  slaveclk1           | |   82  |Biput |  lbusy[1]            |
|   33  |Biput |  local_mode          | |   83  |Biput |  lbusy[2]            |
|   34  |Biput |  gflt_mode           | |   84  |Biput |  lbusy[3]            |
|   35  |Biput |  aclk_on             | |   85  |Biput |  lbusy[4]            |
|   36  |Biput |  hclk_on             | |   86  |Biput |  lbusy[5]            |
|   37  |Biput |  trig_in             | |   87  |Biput |  db[2]               |
|   38  |Biput |  fcstp               | |   88  |Vcc   |                      |
|   39  |Biput |  h_reset             | |   89  |GND   |                      |
|   40  |Biput |  a_reset             | |   90  |GND   |                      |
|   41  |GND   |                      | |   91  |GND   |                      |
|   42  |Biput |  errorout            | |   92  |GND   |                      |
|   43  |Biput |  a_accept            | |   93  |Vcc   |                      |
|   44  |Biput |  cal_busy            | |   94  |Biput |  lerror[1]           |
|   45  |Biput |  testbusy            | |   95  |Biput |  lerror[2]           |
|   46  |Biput |  aclk_fault          | |   96  |Biput |  lerror[3]           |
|   47  |Biput |  hclk_fault          | |   97  |Biput |  lerror[4]           |
|   48  |Biput |  pll_fault           | |   98  |Biput |  lerror[5]           |
|   49  |Biput |  a_abort             | |   99  |Biput |                      |
|   50  |GND   |                      | |  100  |GND   |                      |
+-------+------+----------------------+ +-------+------+----------------------+ 


             Device  1 - MV512_184 -- Pinout for QFP package (continued)

+-------+------+----------------------+ +-------+------+----------------------+ 
|  Pin  | Type |        Signal        | |  Pin  | Type |        Signal        |
+-------+------+----------------------+ +-------+------+----------------------+ 
|  101  |Biput |  ctpdl[0]            | |  151  |GND   |                      |
|  102  |Biput |  ctpdl[1]            | |  152  |In/CLK|                      |
|  103  |Biput |  ctpdl[2]            | |  153  |Biput |  s1dl[0]             |
|  104  |Biput |  ctpdl[3]            | |  154  |Biput |  s1dl[1]             |
|  105  |Biput |  ctpdl[4]            | |  155  |Biput |  s1dl[2]             |
|  106  |Biput |  ctpdl[5]            | |  156  |Biput |  s1dl[3]             |
|  107  |Biput |  ctpdl[6]            | |  157  |Biput |  s1dl[4]             |
|  108  |Biput |  ctpdl[7]            | |  158  |Biput |  s1dl[5]             |
|  109  |Vcc   |                      | |  159  |Biput |  s1dl[6]             |
|  110  |GND   |                      | |  160  |Biput |  s1dl[7]             |
|  111  |Biput |  ctpdl[8]            | |  161  |GND   |                      |
|  112  |Biput |  ctpdl[9]            | |  162  |Biput |  empty_i[2]          |
|  113  |Biput |  ctpdl[10]           | |  163  |Biput |  lf_errormask[1]     |
|  114  |Biput |  ctpdl[11]           | |  164  |Biput |  entestbusy          |
|  115  |Biput |  ctpdl[12]           | |  165  |Biput |  empty_o[1]          |
|  116  |Biput |  ctpdl[13]           | |  166  |Biput |  va_reset            |
|  117  |Biput |  ctpdl[14]           | |  167  |Biput |  empty_i[1]          |
|  118  |Biput |  ctpdl[15]           | |  168  |Biput |  lf_errormask[2]     |
|  119  |Vcc   |                      | |  169  |Biput |                      |
|  120  |GND   |                      | |  170  |GND   |                      |
|  121  |Jtag  |                      | |  171  |Vcc   |                      |
|  122  |Biput |  fctdl[0]            | |  172  |Biput |  empty_i[7]          |
|  123  |Biput |  fctdl[1]            | |  173  |Biput |  db[11]              |
|  124  |Biput |  fctdl[2]            | |  174  |Biput |  empty_i[5]          |
|  125  |Biput |  fctdl[3]            | |  175  |Biput |  db[12]              |
|  126  |Biput |  fctdl[4]            | |  176  |Biput |  empty_i[3]          |
|  127  |Biput |  fctdl[5]            | |  177  |Biput |  db[10]              |
|  128  |Biput |  fctdl[6]            | |  178  |Biput |  empty_i[6]          |
|  129  |Biput |  fctdl[7]            | |  179  |Biput |  empty_i[4]          |
|  130  |Vcc   |                      | |  180  |Jtag  |                      |
|  131  |GND   |                      | |  181  |GND   |                      |
|  132  |Biput |  hcdl[0]             | |  182  |Vcc   |                      |
|  133  |Biput |  hcdl[1]             | |  183  |Biput |                      |
|  134  |Biput |  hcdl[2]             | |  184  |Biput |  db[14]              |
|  135  |Biput |  hcdl[3]             | |  185  |Biput |                      |
|  136  |Biput |  hcdl[4]             | |  186  |Biput |  db[15]              |
|  137  |Biput |  hcdl[5]             | |  187  |Biput |                      |
|  138  |Biput |  hcdl[6]             | |  188  |Biput |  db[1]               |
|  139  |Biput |  hcdl[7]             | |  189  |Biput |                      |
|  140  |GND   |                      | |  190  |Biput |                      |
|  141  |Biput |  lf_error[1]         | |  191  |GND   |                      |
|  142  |Biput |  lf_error[2]         | |  192  |Vcc   |                      |
|  143  |Biput |  lf_error[3]         | |  193  |Biput |                      |
|  144  |Biput |  lf_error[4]         | |  194  |Biput |  lf_errormask[4]     |
|  145  |Biput |  lf_error[5]         | |  195  |Biput |  clrtestbusy         |
|  146  |Biput |  lbusymask[2]        | |  196  |Biput |  empty_o[2]          |
|  147  |Biput |  lf_errormask[3]     | |  197  |Biput |  vcalibrate          |
|  148  |Biput |  lf_errormask[5]     | |  198  |Biput |                      |
|  149  |In/CLK|                      | |  199  |Biput |  empty_i[0]          |
|  150  |Vcc   |                      | |  200  |Biput |  lerrormask[5]       |
+-------+------+----------------------+ +-------+------+----------------------+ 


             Device  1 - MV512_184 -- Pinout for QFP package (continued)

+-------+------+----------------------+ +-------+------+----------------------+ 
|  Pin  | Type |        Signal        | |  Pin  | Type |        Signal        |
+-------+------+----------------------+ +-------+------+----------------------+ 
|  201  |GND   |                      | |  221  |Biput |  s23[1]              |
|  202  |Biput |                      | |  222  |Biput |  vh_reset            |
|  203  |Biput |                      | |  223  |Biput |  lbusymask[5]        |
|  204  |Biput |  db[9]               | |  224  |Biput |  lerrormask[1]       |
|  205  |Biput |                      | |  225  |Biput |  vf_error            |
|  206  |Biput |                      | |  226  |Biput |  vt_error            |
|  207  |Biput |  db[13]              | |  227  |Biput |  s13[2]              |
|  208  |Vcc   |                      | |  228  |Biput |  vmoa_reset          |
|  209  |GND   |                      | |  229  |Vcc   |                      |
|  210  |GND   |                      | |  230  |GND   |                      |
|  211  |GND   |                      | |  231  |Biput |  s23[0]              |
|  212  |GND   |                      | |  232  |Biput |  db[3]               |
|  213  |Vcc   |                      | |  233  |Biput |  rosysout_s34[1]     |
|  214  |Biput |  vbusy               | |  234  |Biput |  s34[0]              |
|  215  |Biput |  rosysout_s23[1]     | |  235  |Biput |  s13[1]              |
|  216  |Biput |  db[4]               | |  236  |Biput |  db[5]               |
|  217  |Biput |  s13[0]              | |  237  |Biput |  rosysout_s34[0]     |
|  218  |Biput |  rosysout_s23[0]     | |  238  |Biput |  m_busy_s34          |
|  219  |Biput |  lbusymask[4]        | |  239  |Vcc   |                      |
|  220  |GND   |                      | |  240  |GND   |                      |
+-------+------+----------------------+ +-------+------+----------------------+ 


DEVICE SELECTION: 

      Device         Man  Fam Pack Temp   ICC     TPD     Fmax    Price   User

==> M5-512/184-7HC   AMD CMOS QFP  COM   999.9ma   9.5ns 105.0MHz $  0.00   0 0
PLDocument:  Y:\clock\zeus\master\pld3\pld3.doc
                  WIRELIST  Mon Feb 28 15:13:15 2000

  +------------------+-------------------+-------+
  |      Signal      |       Device      |  Pin  |
  +------------------+-------------------+-------+
  | noa_rst          | MV512_184_1       |   75  |
  | slaveclk1        | MV512_184_1       |   32  |
  | bwriteb          | MV512_184_1       |   79  |
  | breadb           | MV512_184_1       |   73  |
  | reg06            | MV512_184_1       |   52  |
  | reg08            | MV512_184_1       |   53  |
  | reg0A            | MV512_184_1       |   54  |
  | reg0C            | MV512_184_1       |   55  |
  | reg0E            | MV512_184_1       |   56  |
  | reg10            | MV512_184_1       |   57  |
  | reg12            | MV512_184_1       |   58  |
  | reg14            | MV512_184_1       |   59  |
  | leb2             | MV512_184_1       |   29  |
  | db[15]           | MV512_184_1       |  186  |
  | db[14]           | MV512_184_1       |  184  |
  | db[13]           | MV512_184_1       |  207  |
  | db[12]           | MV512_184_1       |  175  |
  | db[11]           | MV512_184_1       |  173  |
  | db[10]           | MV512_184_1       |  177  |
  | db[9]            | MV512_184_1       |  204  |
  | db[8]            | MV512_184_1       |    7  |
  | db[7]            | MV512_184_1       |    9  |
  | db[6]            | MV512_184_1       |   19  |
  | db[5]            | MV512_184_1       |  236  |
  | db[4]            | MV512_184_1       |  216  |
  | db[3]            | MV512_184_1       |  232  |
  | db[2]            | MV512_184_1       |   87  |
  | db[1]            | MV512_184_1       |  188  |
  | db[0]            | MV512_184_1       |   69  |
  | s13[3]           | MV512_184_1       |   74  |
  | s13[2]           | MV512_184_1       |  227  |
  | s13[1]           | MV512_184_1       |  235  |
  | s13[0]           | MV512_184_1       |  217  |
  | s23[1]           | MV512_184_1       |  221  |
  | s23[0]           | MV512_184_1       |  231  |
  | s34[0]           | MV512_184_1       |  234  |
  | empty_i[7]       | MV512_184_1       |  172  |
  | empty_i[6]       | MV512_184_1       |  178  |
  | empty_i[5]       | MV512_184_1       |  174  |
  | empty_i[4]       | MV512_184_1       |  179  |
  | empty_i[3]       | MV512_184_1       |  176  |
  | empty_i[2]       | MV512_184_1       |  162  |
  | empty_i[1]       | MV512_184_1       |  167  |
  | empty_i[0]       | MV512_184_1       |  199  |
  | empty_o[2]       | MV512_184_1       |  196  |
  | empty_o[1]       | MV512_184_1       |  165  |
  | empty_o[0]       | MV512_184_1       |   78  |
  | rosysout_s23[1]  | MV512_184_1       |  215  |
  | rosysout_s23[0]  | MV512_184_1       |  218  |
  | rosysout_s34[1]  | MV512_184_1       |  233  |
  | rosysout_s34[0]  | MV512_184_1       |  237  |
  +------------------+-------------------+-------+


  +------------------+-------------------+-------+
  |      Signal      |       Device      |  Pin  |
  +------------------+-------------------+-------+
  | clrtestbusy      | MV512_184_1       |  195  |
  | entestbusy       | MV512_184_1       |  164  |
  | va_reset         | MV512_184_1       |  166  |
  | vh_reset         | MV512_184_1       |  222  |
  | vcalibrate       | MV512_184_1       |  197  |
  | vtrigger         | MV512_184_1       |   26  |
  | envar_trig       | MV512_184_1       |    8  |
  | verror           | MV512_184_1       |   27  |
  | vt_error         | MV512_184_1       |  226  |
  | vf_error         | MV512_184_1       |  225  |
  | vbusy            | MV512_184_1       |  214  |
  | vmoa_reset       | MV512_184_1       |  228  |
  | wrcontr1         | MV512_184_1       |   80  |
  | local_mode       | MV512_184_1       |   33  |
  | gflt_mode        | MV512_184_1       |   34  |
  | aclk_on          | MV512_184_1       |   35  |
  | hclk_on          | MV512_184_1       |   36  |
  | errorout         | MV512_184_1       |   42  |
  | trig_in          | MV512_184_1       |   37  |
  | fcstp            | MV512_184_1       |   38  |
  | h_reset          | MV512_184_1       |   39  |
  | a_reset          | MV512_184_1       |   40  |
  | lasttrig_abort   | MV512_184_1       |   70  |
  | a_accept         | MV512_184_1       |   43  |
  | cal_busy         | MV512_184_1       |   44  |
  | testbusy         | MV512_184_1       |   45  |
  | m_busy_s34       | MV512_184_1       |  238  |
  | aclk_fault       | MV512_184_1       |   46  |
  | hclk_fault       | MV512_184_1       |   47  |
  | pll_fault        | MV512_184_1       |   48  |
  | a_abort          | MV512_184_1       |   49  |
  | busy[5]          | MV512_184_1       |    6  |
  | busy[4]          | MV512_184_1       |    5  |
  | busy[3]          | MV512_184_1       |    4  |
  | busy[2]          | MV512_184_1       |    3  |
  | busy[1]          | MV512_184_1       |    2  |
  | error[5]         | MV512_184_1       |   16  |
  | error[4]         | MV512_184_1       |   15  |
  | error[3]         | MV512_184_1       |   14  |
  | error[2]         | MV512_184_1       |   13  |
  | error[1]         | MV512_184_1       |   12  |
  | f_error[5]       | MV512_184_1       |   25  |
  | f_error[4]       | MV512_184_1       |   24  |
  | f_error[3]       | MV512_184_1       |   23  |
  | f_error[2]       | MV512_184_1       |   22  |
  | f_error[1]       | MV512_184_1       |   21  |
  | lf_error[5]      | MV512_184_1       |  145  |
  | lf_error[4]      | MV512_184_1       |  144  |
  | lf_error[3]      | MV512_184_1       |  143  |
  | lf_error[2]      | MV512_184_1       |  142  |
  | lf_error[1]      | MV512_184_1       |  141  |
  +------------------+-------------------+-------+


  +------------------+-------------------+-------+
  |      Signal      |       Device      |  Pin  |
  +------------------+-------------------+-------+
  | lerror[5]        | MV512_184_1       |   98  |
  | lerror[4]        | MV512_184_1       |   97  |
  | lerror[3]        | MV512_184_1       |   96  |
  | lerror[2]        | MV512_184_1       |   95  |
  | lerror[1]        | MV512_184_1       |   94  |
  | lbusy[5]         | MV512_184_1       |   86  |
  | lbusy[4]         | MV512_184_1       |   85  |
  | lbusy[3]         | MV512_184_1       |   84  |
  | lbusy[2]         | MV512_184_1       |   83  |
  | lbusy[1]         | MV512_184_1       |   82  |
  | lf_errormask[5]  | MV512_184_1       |  148  |
  | lf_errormask[4]  | MV512_184_1       |  194  |
  | lf_errormask[3]  | MV512_184_1       |  147  |
  | lf_errormask[2]  | MV512_184_1       |  168  |
  | lf_errormask[1]  | MV512_184_1       |  163  |
  | lerrormask[5]    | MV512_184_1       |  200  |
  | lerrormask[4]    | MV512_184_1       |   18  |
  | lerrormask[3]    | MV512_184_1       |   17  |
  | lerrormask[2]    | MV512_184_1       |   28  |
  | lerrormask[1]    | MV512_184_1       |  224  |
  | lbusymask[5]     | MV512_184_1       |  223  |
  | lbusymask[4]     | MV512_184_1       |  219  |
  | lbusymask[3]     | MV512_184_1       |   76  |
  | lbusymask[2]     | MV512_184_1       |  146  |
  | lbusymask[1]     | MV512_184_1       |   77  |
  | fctdl[7]         | MV512_184_1       |  129  |
  | fctdl[6]         | MV512_184_1       |  128  |
  | fctdl[5]         | MV512_184_1       |  127  |
  | fctdl[4]         | MV512_184_1       |  126  |
  | fctdl[3]         | MV512_184_1       |  125  |
  | fctdl[2]         | MV512_184_1       |  124  |
  | fctdl[1]         | MV512_184_1       |  123  |
  | fctdl[0]         | MV512_184_1       |  122  |
  | cctdl[5]         | MV512_184_1       |   68  |
  | cctdl[4]         | MV512_184_1       |   67  |
  | cctdl[3]         | MV512_184_1       |   66  |
  | cctdl[2]         | MV512_184_1       |   65  |
  | cctdl[1]         | MV512_184_1       |   64  |
  | cctdl[0]         | MV512_184_1       |   63  |
  | s1dl[7]          | MV512_184_1       |  160  |
  | s1dl[6]          | MV512_184_1       |  159  |
  | s1dl[5]          | MV512_184_1       |  158  |
  | s1dl[4]          | MV512_184_1       |  157  |
  | s1dl[3]          | MV512_184_1       |  156  |
  | s1dl[2]          | MV512_184_1       |  155  |
  | s1dl[1]          | MV512_184_1       |  154  |
  | s1dl[0]          | MV512_184_1       |  153  |
  | hcdl[7]          | MV512_184_1       |  139  |
  | hcdl[6]          | MV512_184_1       |  138  |
  | hcdl[5]          | MV512_184_1       |  137  |
  | hcdl[4]          | MV512_184_1       |  136  |
  +------------------+-------------------+-------+


  +------------------+-------------------+-------+
  |      Signal      |       Device      |  Pin  |
  +------------------+-------------------+-------+
  | hcdl[3]          | MV512_184_1       |  135  |
  | hcdl[2]          | MV512_184_1       |  134  |
  | hcdl[1]          | MV512_184_1       |  133  |
  | hcdl[0]          | MV512_184_1       |  132  |
  | ctpdl[15]        | MV512_184_1       |  118  |
  | ctpdl[14]        | MV512_184_1       |  117  |
  | ctpdl[13]        | MV512_184_1       |  116  |
  | ctpdl[12]        | MV512_184_1       |  115  |
  | ctpdl[11]        | MV512_184_1       |  114  |
  | ctpdl[10]        | MV512_184_1       |  113  |
  | ctpdl[9]         | MV512_184_1       |  112  |
  | ctpdl[8]         | MV512_184_1       |  111  |
  | ctpdl[7]         | MV512_184_1       |  108  |
  | ctpdl[6]         | MV512_184_1       |  107  |
  | ctpdl[5]         | MV512_184_1       |  106  |
  | ctpdl[4]         | MV512_184_1       |  105  |
  | ctpdl[3]         | MV512_184_1       |  104  |
  | ctpdl[2]         | MV512_184_1       |  103  |
  | ctpdl[1]         | MV512_184_1       |  102  |
  | ctpdl[0]         | MV512_184_1       |  101  |
  +------------------+-------------------+-------+