"=================================================================================================== #TITLE 'ZEUS MVD C&C MASTER, PLD2, GFLT INTERFACE & RETURNS'; #ENGINEER 'Martin Postranecky / Dominic A Hayes'; #COMPANY 'University College London'; #COMMENT ''; "=================================================================================================== " "MODIFIED "15NOV99 bwrite_s12 replaces bwriteb as INPUT (from PLD1). " bwriteb (=bwrite_s12) now output (to PLD3) on same pin (as original bwrite input). "11jan00 leb2 -> /leb2. " empty o/p's set to 0. "13jan00 trigger increments b_counter after counter contents shifted into reg00 " (acceptclk[3] clock phases swapped). "14jan00 XOR "(+)" instead of OR in b_clk to complete 13jan mod. "09feb00 c counter reset by 219 instead of 220. "17feb00 ttypout output to pld4 as ttypout_s24 on spare connections. "25feb00 rosysout output to pld4 via pld3 as rosysout_s2/34. "28feb00 new o/p local_bcn0_s24 (= c_counter reset). "29feb00 reg0 and reg1 testenclk1 -> testenout & acceptclk1 -> acceptout. " "=================================================================================================== " SIGNAL DECLARATIONS "=================================================================================================== LOW_TRUE INPUT noa_rst; LOW_TRUE INPUT bwrite_s12; "bwrite from PLD1. LOW_TRUE OUTPUT bwriteb; "bwrite to PLD3. LOW_TRUE INPUT breadb; LOW_TRUE INPUT reg00, reg02, reg04; LOW_TRUE INPUT leb2; INPUT clk_1, clk_2, clk_3; INPUT da[1..0]; "backplane data multiplex signals. INPUT acceptclk[3..1]; "acceptclk[2] not used or i/p. INPUT testenclk1; INPUT wrcontr1; "1 = LOCAL (VME) mode; 0 = GFLT mode. INPUT empty_g[9]; "empty slots in registers. "--------------------------------------------------------------------------------------- "Register00 (COUNTER WRITE / VME READ) INPUT fltn[7..0]; INPUT gbcn[7..0]; NODE register00[15..0] CLOCKED_BY reg00_clk RESET_BY noa_rst DEFAULT_TO LAST_VALUE; NODE reg00_clk; "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register02 (GFLT WRITE, VME READ/WRITE) INPUT testen; INPUT ttyp[2..0]; INPUT rosys[1..0]; INPUT roamb[1..0]; INPUT rousr[2..0]; INPUT gfltabort; INPUT gfltaccept; NODE register02c[15..12] "15,14 Empty bits. CLOCKED_BY reg02c_clk RESET_BY noa_rst DEFAULT_TO LAST_VALUE; NODE reg02c_clk; NODE register02b[11..5] CLOCKED_BY reg02b_clk RESET_BY noa_rst DEFAULT_TO LAST_VALUE; NODE reg02b_clk; NODE register02a[4..2] CLOCKED_BY reg02a_clk RESET_BY noa_rst DEFAULT_TO LAST_VALUE; NODE reg02a_clk; NODE register02aa[1..0] "0 Empty bit. CLOCKED_BY reg02c_clk RESET_BY noa_rst DEFAULT_TO LAST_VALUE; OUTPUT testenout, ttypout[2..0], ttypout_s24[2..0], acceptout, abortout; OUTPUT local_bcn0_s24 DEFAULT_TO 0; "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "Register04 (GFLT WRITE / VME READ) INPUT busyout; INPUT f_errorout; INPUT t_errorout; INPUT bplane_accept, bplane_abort, bplane_reset, bplane_error, bplane_f_error, bplane_busy, bplane_empty; NODE register04[15..0] "8..6, 2..0 Empty bits. CLOCKED_BY reg04_clk RESET_BY noa_rst DEFAULT_TO LAST_VALUE; NODE reg04_clk; OUTPUT busy, f_error, t_error; "--------------------------------------------------------------------------------------- "--------------------------------------------------------------------------------------- "COUNTERS NODE b_counter[7..0] "FLTN counter CLOCKED_BY b_clk RESET_BY noa_rst DEFAULT_TO LAST_VALUE; NODE b_clk; NODE c_counter[7..0] "GBCN counter. CLOCKED_BY c_clk RESET_BY noa_rst DEFAULT_TO LAST_VALUE; NODE c_clk; "--------------------------------------------------------------------------------------- NODE pre_load, dboe; BIPUT db[15..0] "VME databus. ENABLED_BY dboe; OUTPUT mdb[7..0]; "multiplexed bus to backplane. "SPARE I/O "--------- INPUT s12[3]; "spare outputs was 4, s12[3] used by bwrite_s12. INPUT s23[2]; "spare outputs. was 4 now 2, 2 used by rosysout_s23 to pld3. " INPUT s24[0]; "spare outputs. was 4, 3 now used to send ttypout to pld4. " 1 used by local_bcn0_s24. "COMP_OFF "============================= " *** TESTING ONLY *** NODE register02[16]; register02 = [ register02c, register02b, register02a, register02aa ]; "============================= "COMP_ON "ROSYSOUT routing "---------------- OUTPUT rosysout_s23[1..0]; "output to pld4 via pld3 using spare lines. "=================================================================================================== " LOGIC "=================================================================================================== bwriteb = bwrite_s12; "bwrite pass-thru (to PLD3). dboe = breadb AND (reg00 OR reg02 OR reg04); "databus output enable. " Dual source register clocking "------------------------------- " GFLT mode clocking LOCAL mode clocking " -------------------- --------------------- reg00_clk = ( acceptout AND /wrcontr1) OR ( acceptclk[3] AND wrcontr1); reg02a_clk = ( testenout AND /wrcontr1) OR ( /leb2 AND wrcontr1); reg02b_clk = ( acceptout AND /wrcontr1) OR ( /leb2 AND wrcontr1); reg02c_clk = ( clk_1 AND /wrcontr1) OR ( /leb2 AND wrcontr1); " BOTH MODES " ------------ reg04_clk = clk_3; b_clk = acceptclk[3] OR (/leb2 AND pre_load); "clocks all the time, o/p into reg00 c_clk = (clk_2 AND /pre_load) OR (/leb2 AND pre_load); " disabled when in GFLT mode. " Assigning register inputs "--------------------------- IF (/wrcontr1) THEN "GFLT writes to Registers. register00[15..0] = [ gbcn[7..0], fltn[7..0] ]; register02c[15..12] = [ 0, 0, gfltaccept, gfltabort ] ; " empty_g[2], empty_g[1], register02b[11..5] = [ rousr[2..0], roamb[1..0], rosys[1..0] ]; register02a[4..2] = ttyp[2..0]; register02aa[1..0] = [ testen, 0 ]; " empty_g[0] ELSIF (wrcontr1) THEN register00[15..0] = [ c_counter[7..0], b_counter[7..0] ]; "counters o/p at Register00 input. IF (reg02) THEN register02c[15..12] = db[15..12]; "15,14 empty register02b[11..5] = db[11..5]; "VME WRITES to Register02 register02a[4..2] = db[4..2]; register02aa[1..0] = db[1..0]; "0 empty END IF; END IF; "This moved outside of IF structure. 2/6/99. register04[15..0] = [ bplane_accept, bplane_abort, bplane_reset, bplane_error, bplane_f_error, bplane_busy, bplane_empty, 0,0,0, " empty_g[8..6], t_errorout, f_errorout, busyout, 0,0,0 ]; " empty_g[2..0] ]; "------------------------------- " Assigning data to the vme databus biput db "-------------------------------------------- IF (breadb) THEN IF (reg00) THEN db = register00; "VME READs register00. ELSIF (reg02) THEN db[15..0] = [ register02c, "VME READs register02. register02b, register02a, register02aa ]; "[15..14, 0] empty bits ELSIF (reg04) THEN db[15..0] = register04; "VME READs register04. [15..6, 0] empty. END IF; END IF; "-------------------------------------------- " preload counters & " c_counter synchronous reset "----------------------------- pre_load = wrcontr1 AND reg00 AND bwrite_s12; IF (pre_load) THEN b_counter = db[7..0]; "counters pre-loaded from VME. c_counter = db[15..8]; " ELSE IF (c_counter = 219) THEN c_counter = 0; "c_counter reset. local_bcn0_s24 = 1; ELSE c_counter = c_counter .+. 1; "c_counter increments. END IF; b_counter = b_counter .+. 1; "b_counter increments. END IF; "----------------------------- " Assigning the multiplexed output mdb to backplane "--------------------------------------------------- IF (/da[1] AND /da[0]) THEN mdb[0] = 0; "LSB set to 0. mdb[7..1] = register02b; "rosys, roamb, rousr. (A) ELSIF (da[1] AND /da[0]) THEN mdb = register00[7..0]; "fltn. (B) ELSIF (/da[1] AND da[0]) THEN mdb = register00[15..8]; "gbcn. (C) ELSIF (da[1] AND da[0]) THEN mdb = 0; "mdb DISabled by a1 AND a0. (Not tristated.) END IF; "--------------------------------------------------- "From register 02 "---------------- testenout = register02aa[1]; ttypout[2..0] = register02a[4..2]; "original ttyp outputs (unchanged). ttypout_s24[2..0] = ttypout[2..0]; "ttypout outputs to pld4 using spare connections. rosysout_s23[1..0] = register02b[6..5]; abortout = register02c[12]; acceptout = register02c[13]; "From register 04 "---------------- busy = register04[3]; f_error = register04[4]; t_error = register04[5]; "==================================================================================================