PLDocument: Y:\clock\zeus\master\pld2\pld2.doc TITLE PAGE Tue Feb 29 14:58:16 2000 A MACHXL6.2.1.11 - (c) Copyright MINC Incorporated 1987-1998 ============================================================================== TITLE : ZEUS MVD C&C MASTER, PLD2, GFLT INTERFACE & RETURNS FILE : Y:\clock\zeus\master\pld2\pld2.mpf DATE : Thu Jun 04 02:36:00 1970 ENGINEER : Martin Postranecky / Dominic A Hayes COMPANY : University College London ============================================================================== MODULES : Document Generator 3.70 File Handler 6.2 Language Compiler 3.83 Architectural Optimizer 3.110 Device Lib Scan 3.2 Device Library 3.17 Device Partition 3.21 Device Fusemap 3.4 SWITCH VALUES : (Value in parenthesis represents batch mode switch value) PLCOMP PRODUCT TERM LIMIT : 128 PLOPT PRODUCT TERM LIMIT : 128 PLOPT REDUCTION : Espresso (1) NODE GENERATION : Procedure Instantiation Arithmetic and Relational Operators (1) PLDocument: Y:\clock\zeus\master\pld2\pld2.doc EQUATIONS Tue Feb 29 14:58:16 2000 EQUATIONS FOR SYSTEM INPUT SIGNALS (70) : LOW_TRUE noa_rst LOW_TRUE bwrite_s12 LOW_TRUE breadb LOW_TRUE reg00 LOW_TRUE reg02 LOW_TRUE reg04 LOW_TRUE leb2 clk_1 clk_2 clk_3 da[1..0] acceptclk[3..1] testenclk1 wrcontr1 empty_g[8..0] fltn[7..0] gbcn[7..0] testen ttyp[2..0] rosys[1..0] roamb[1..0] rousr[2..0] gfltabort gfltaccept busyout f_errorout t_errorout bplane_accept bplane_abort bplane_reset bplane_error bplane_f_error bplane_busy bplane_empty s12[2..0] s23[1..0] OUTPUT SIGNALS (40) : LOW_TRUE bwriteb acceptout abortout rosysout_s23[1..0] ttypout[2..0] testenout ttypout_s24[2..0] local_bcn0_s24 t_error f_error busy db[15..0] mdb[7..0] PHYSICAL NODE SIGNALS (63) : register00[15..0] reg00_clk register02c[15..14] reg02c_clk register02b[11..7] reg02b_clk reg02a_clk register02aa[0] register04[15..6] register04[2..0] b_counter[7..0] b_clk c_counter[7..0] c_clk dboe add_carry-4 add_carry-7 add_carry-13 REDUCED EQUATIONS: bwriteb.EQN = bwrite_s12 ; "(1 term, 1 symbol) register00[15].D = c_counter[7]*wrcontr1 + gbcn[7]*/wrcontr1 ; "(2 terms, 3 symbols) register00[15].CLK = reg00_clk ; "(1 term, 1 symbol) register00[15].RESET = noa_rst ; "(1 term, 1 symbol) register00[14].D = c_counter[6]*wrcontr1 + gbcn[6]*/wrcontr1 ; "(2 terms, 3 symbols) register00[14].CLK = reg00_clk ; "(1 term, 1 symbol) register00[14].RESET = noa_rst ; "(1 term, 1 symbol) register00[13].D = c_counter[5]*wrcontr1 + gbcn[5]*/wrcontr1 ; "(2 terms, 3 symbols) register00[13].CLK = reg00_clk ; "(1 term, 1 symbol) register00[13].RESET = noa_rst ; "(1 term, 1 symbol) register00[12].D = c_counter[4]*wrcontr1 + gbcn[4]*/wrcontr1 ; "(2 terms, 3 symbols) register00[12].CLK = reg00_clk ; "(1 term, 1 symbol) register00[12].RESET = noa_rst ; "(1 term, 1 symbol) register00[11].D = c_counter[3]*wrcontr1 + gbcn[3]*/wrcontr1 ; "(2 terms, 3 symbols) register00[11].CLK = reg00_clk ; "(1 term, 1 symbol) register00[11].RESET = noa_rst ; "(1 term, 1 symbol) register00[10].D = c_counter[2]*wrcontr1 + gbcn[2]*/wrcontr1 ; "(2 terms, 3 symbols) register00[10].CLK = reg00_clk ; "(1 term, 1 symbol) register00[10].RESET = noa_rst ; "(1 term, 1 symbol) register00[9].D = c_counter[1]*wrcontr1 + gbcn[1]*/wrcontr1 ; "(2 terms, 3 symbols) register00[9].CLK = reg00_clk ; "(1 term, 1 symbol) register00[9].RESET = noa_rst ; "(1 term, 1 symbol) register00[8].D = c_counter[0]*wrcontr1 + gbcn[0]*/wrcontr1 ; "(2 terms, 3 symbols) register00[8].CLK = reg00_clk ; "(1 term, 1 symbol) register00[8].RESET = noa_rst ; "(1 term, 1 symbol) register00[7].D = b_counter[7]*wrcontr1 + fltn[7]*/wrcontr1 ; "(2 terms, 3 symbols) register00[7].CLK = reg00_clk ; "(1 term, 1 symbol) register00[7].RESET = noa_rst ; "(1 term, 1 symbol) register00[6].D = b_counter[6]*wrcontr1 + fltn[6]*/wrcontr1 ; "(2 terms, 3 symbols) register00[6].CLK = reg00_clk ; "(1 term, 1 symbol) register00[6].RESET = noa_rst ; "(1 term, 1 symbol) register00[5].D = b_counter[5]*wrcontr1 + fltn[5]*/wrcontr1 ; "(2 terms, 3 symbols) register00[5].CLK = reg00_clk ; "(1 term, 1 symbol) register00[5].RESET = noa_rst ; "(1 term, 1 symbol) register00[4].D = b_counter[4]*wrcontr1 + fltn[4]*/wrcontr1 ; "(2 terms, 3 symbols) register00[4].CLK = reg00_clk ; "(1 term, 1 symbol) register00[4].RESET = noa_rst ; "(1 term, 1 symbol) register00[3].D = b_counter[3]*wrcontr1 + fltn[3]*/wrcontr1 ; "(2 terms, 3 symbols) register00[3].CLK = reg00_clk ; "(1 term, 1 symbol) register00[3].RESET = noa_rst ; "(1 term, 1 symbol) register00[2].D = b_counter[2]*wrcontr1 + fltn[2]*/wrcontr1 ; "(2 terms, 3 symbols) register00[2].CLK = reg00_clk ; "(1 term, 1 symbol) register00[2].RESET = noa_rst ; "(1 term, 1 symbol) register00[1].D = b_counter[1]*wrcontr1 + fltn[1]*/wrcontr1 ; "(2 terms, 3 symbols) register00[1].CLK = reg00_clk ; "(1 term, 1 symbol) register00[1].RESET = noa_rst ; "(1 term, 1 symbol) register00[0].D = b_counter[0]*wrcontr1 + fltn[0]*/wrcontr1 ; "(2 terms, 3 symbols) register00[0].CLK = reg00_clk ; "(1 term, 1 symbol) register00[0].RESET = noa_rst ; "(1 term, 1 symbol) reg00_clk.EQN = acceptclk[3]*wrcontr1 + acceptout*/wrcontr1 ; "(2 terms, 3 symbols) register02c[15].D = db[15]*reg02*wrcontr1 + /reg02*register02c[15]*wrcontr1 ; "(2 terms, 4 symbols) register02c[15].CLK = reg02c_clk ; "(1 term, 1 symbol) register02c[15].RESET = noa_rst ; "(1 term, 1 symbol) register02c[14].D = db[14]*reg02*wrcontr1 + /reg02*register02c[14]*wrcontr1 ; "(2 terms, 4 symbols) register02c[14].CLK = reg02c_clk ; "(1 term, 1 symbol) register02c[14].RESET = noa_rst ; "(1 term, 1 symbol) acceptout.D = db[13]*reg02*wrcontr1 + gfltaccept*/wrcontr1 + /reg02*acceptout*wrcontr1 ; "(3 terms, 5 symbols) acceptout.CLK = reg02c_clk ; "(1 term, 1 symbol) acceptout.RESET = noa_rst ; "(1 term, 1 symbol) abortout.D = db[12]*reg02*wrcontr1 + gfltabort*/wrcontr1 + /reg02*abortout*wrcontr1 ; "(3 terms, 5 symbols) abortout.CLK = reg02c_clk ; "(1 term, 1 symbol) abortout.RESET = noa_rst ; "(1 term, 1 symbol) reg02c_clk.EQN = clk_1*/wrcontr1 + /leb2*wrcontr1 ; "(2 terms, 3 symbols) register02b[11].D = db[11]*reg02*wrcontr1 + /reg02*register02b[11]*wrcontr1 + rousr[2]*/wrcontr1 ; "(3 terms, 5 symbols) register02b[11].CLK = reg02b_clk ; "(1 term, 1 symbol) register02b[11].RESET = noa_rst ; "(1 term, 1 symbol) register02b[10].D = db[10]*reg02*wrcontr1 + /reg02*register02b[10]*wrcontr1 + rousr[1]*/wrcontr1 ; "(3 terms, 5 symbols) register02b[10].CLK = reg02b_clk ; "(1 term, 1 symbol) register02b[10].RESET = noa_rst ; "(1 term, 1 symbol) register02b[9].D = db[9]*reg02*wrcontr1 + /reg02*register02b[9]*wrcontr1 + rousr[0]*/wrcontr1 ; "(3 terms, 5 symbols) register02b[9].CLK = reg02b_clk ; "(1 term, 1 symbol) register02b[9].RESET = noa_rst ; "(1 term, 1 symbol) register02b[8].D = db[8]*reg02*wrcontr1 + /reg02*register02b[8]*wrcontr1 + roamb[1]*/wrcontr1 ; "(3 terms, 5 symbols) register02b[8].CLK = reg02b_clk ; "(1 term, 1 symbol) register02b[8].RESET = noa_rst ; "(1 term, 1 symbol) register02b[7].D = db[7]*reg02*wrcontr1 + /reg02*register02b[7]*wrcontr1 + roamb[0]*/wrcontr1 ; "(3 terms, 5 symbols) register02b[7].CLK = reg02b_clk ; "(1 term, 1 symbol) register02b[7].RESET = noa_rst ; "(1 term, 1 symbol) rosysout_s23[1].D = db[6]*reg02*wrcontr1 + /reg02*rosysout_s23[1]*wrcontr1 + rosys[1]*/wrcontr1 ; "(3 terms, 5 symbols) rosysout_s23[1].CLK = reg02b_clk ; "(1 term, 1 symbol) rosysout_s23[1].RESET = noa_rst ; "(1 term, 1 symbol) rosysout_s23[0].D = db[5]*reg02*wrcontr1 + /reg02*rosysout_s23[0]*wrcontr1 + rosys[0]*/wrcontr1 ; "(3 terms, 5 symbols) rosysout_s23[0].CLK = reg02b_clk ; "(1 term, 1 symbol) rosysout_s23[0].RESET = noa_rst ; "(1 term, 1 symbol) reg02b_clk.EQN = /leb2*wrcontr1 + acceptout*/wrcontr1 ; "(2 terms, 3 symbols) ttypout[2].D = db[4]*reg02*wrcontr1 + /reg02*ttypout[2]*wrcontr1 + ttyp[2]*/wrcontr1 ; "(3 terms, 5 symbols) ttypout[2].CLK = reg02a_clk ; "(1 term, 1 symbol) ttypout[2].RESET = noa_rst ; "(1 term, 1 symbol) ttypout[1].D = db[3]*reg02*wrcontr1 + /reg02*ttypout[1]*wrcontr1 + ttyp[1]*/wrcontr1 ; "(3 terms, 5 symbols) ttypout[1].CLK = reg02a_clk ; "(1 term, 1 symbol) ttypout[1].RESET = noa_rst ; "(1 term, 1 symbol) ttypout[0].D = db[2]*reg02*wrcontr1 + /reg02*ttypout[0]*wrcontr1 + ttyp[0]*/wrcontr1 ; "(3 terms, 5 symbols) ttypout[0].CLK = reg02a_clk ; "(1 term, 1 symbol) ttypout[0].RESET = noa_rst ; "(1 term, 1 symbol) reg02a_clk.EQN = /leb2*wrcontr1 + testenout*/wrcontr1 ; "(2 terms, 3 symbols) testenout.D = db[1]*reg02*wrcontr1 + /reg02*testenout*wrcontr1 + testen*/wrcontr1 ; "(3 terms, 5 symbols) testenout.CLK = reg02c_clk ; "(1 term, 1 symbol) testenout.RESET = noa_rst ; "(1 term, 1 symbol) register02aa[0].D = db[0]*reg02*wrcontr1 + /reg02*register02aa[0]*wrcontr1 ; "(2 terms, 4 symbols) register02aa[0].CLK = reg02c_clk ; "(1 term, 1 symbol) register02aa[0].RESET = noa_rst ; "(1 term, 1 symbol) ttypout_s24[2].EQN = ttypout[2] ; "(1 term, 1 symbol) ttypout_s24[1].EQN = ttypout[1] ; "(1 term, 1 symbol) ttypout_s24[0].EQN = ttypout[0] ; "(1 term, 1 symbol) local_bcn0_s24.EQN = /bwrite_s12*c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7] + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7]*/reg00 + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7]* /wrcontr1 ; "(3 terms, 11 symbols) register04[15].D = bplane_accept ; "(1 term, 1 symbol) register04[15].CLK = clk_3 ; "(1 term, 1 symbol) register04[15].RESET = noa_rst ; "(1 term, 1 symbol) register04[14].D = bplane_abort ; "(1 term, 1 symbol) register04[14].CLK = clk_3 ; "(1 term, 1 symbol) register04[14].RESET = noa_rst ; "(1 term, 1 symbol) register04[13].D = bplane_reset ; "(1 term, 1 symbol) register04[13].CLK = clk_3 ; "(1 term, 1 symbol) register04[13].RESET = noa_rst ; "(1 term, 1 symbol) register04[12].D = bplane_error ; "(1 term, 1 symbol) register04[12].CLK = clk_3 ; "(1 term, 1 symbol) register04[12].RESET = noa_rst ; "(1 term, 1 symbol) register04[11].D = bplane_f_error ; "(1 term, 1 symbol) register04[11].CLK = clk_3 ; "(1 term, 1 symbol) register04[11].RESET = noa_rst ; "(1 term, 1 symbol) register04[10].D = bplane_busy ; "(1 term, 1 symbol) register04[10].CLK = clk_3 ; "(1 term, 1 symbol) register04[10].RESET = noa_rst ; "(1 term, 1 symbol) register04[9].D = bplane_empty ; "(1 term, 1 symbol) register04[9].CLK = clk_3 ; "(1 term, 1 symbol) register04[9].RESET = noa_rst ; "(1 term, 1 symbol) register04[8].D = 0 ; "(1 term, 0 symbols) register04[8].CLK = clk_3 ; "(1 term, 1 symbol) register04[8].RESET = noa_rst ; "(1 term, 1 symbol) register04[7].D = 0 ; "(1 term, 0 symbols) register04[7].CLK = clk_3 ; "(1 term, 1 symbol) register04[7].RESET = noa_rst ; "(1 term, 1 symbol) register04[6].D = 0 ; "(1 term, 0 symbols) register04[6].CLK = clk_3 ; "(1 term, 1 symbol) register04[6].RESET = noa_rst ; "(1 term, 1 symbol) t_error.D = t_errorout ; "(1 term, 1 symbol) t_error.CLK = clk_3 ; "(1 term, 1 symbol) t_error.RESET = noa_rst ; "(1 term, 1 symbol) f_error.D = f_errorout ; "(1 term, 1 symbol) f_error.CLK = clk_3 ; "(1 term, 1 symbol) f_error.RESET = noa_rst ; "(1 term, 1 symbol) busy.D = busyout ; "(1 term, 1 symbol) busy.CLK = clk_3 ; "(1 term, 1 symbol) busy.RESET = noa_rst ; "(1 term, 1 symbol) register04[2].D = 0 ; "(1 term, 0 symbols) register04[2].CLK = clk_3 ; "(1 term, 1 symbol) register04[2].RESET = noa_rst ; "(1 term, 1 symbol) register04[1].D = 0 ; "(1 term, 0 symbols) register04[1].CLK = clk_3 ; "(1 term, 1 symbol) register04[1].RESET = noa_rst ; "(1 term, 1 symbol) register04[0].D = 0 ; "(1 term, 0 symbols) register04[0].CLK = clk_3 ; "(1 term, 1 symbol) register04[0].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[7].T = add_carry-13*b_counter[5]*b_counter[6] */bwrite_s12 + add_carry-13*b_counter[5]* b_counter[6]*/reg00 + add_carry-13*b_counter[5]* b_counter[6]*/wrcontr1 + b_counter[7]*bwrite_s12*/db[7]* reg00*wrcontr1 + /b_counter[7]*bwrite_s12*db[7]* reg00*wrcontr1 ; "(5 terms, 8 symbols) b_counter[7].CLK = b_clk ; "(1 term, 1 symbol) b_counter[7].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[6].T = add_carry-13*b_counter[5]*/bwrite_s12 + add_carry-13*b_counter[5]*/reg00 + add_carry-13*b_counter[5]*/wrcontr1 + b_counter[6]*bwrite_s12*/db[6]* reg00*wrcontr1 + /b_counter[6]*bwrite_s12*db[6]* reg00*wrcontr1 ; "(5 terms, 7 symbols) b_counter[6].CLK = b_clk ; "(1 term, 1 symbol) b_counter[6].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[5].T = add_carry-13*/bwrite_s12 + add_carry-13*/reg00 + add_carry-13*/wrcontr1 + b_counter[5]*bwrite_s12*/db[5]* reg00*wrcontr1 + /b_counter[5]*bwrite_s12*db[5]* reg00*wrcontr1 ; "(5 terms, 6 symbols) b_counter[5].CLK = b_clk ; "(1 term, 1 symbol) b_counter[5].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[4].T = b_counter[0]*b_counter[1]*b_counter[2] *b_counter[3]*/bwrite_s12 + b_counter[0]*b_counter[1]* b_counter[2]*b_counter[3]*/reg00 + b_counter[0]*b_counter[1]* b_counter[2]*b_counter[3]*/wrcontr1 + b_counter[4]*bwrite_s12*/db[4]* reg00*wrcontr1 + /b_counter[4]*bwrite_s12*db[4]* reg00*wrcontr1 ; "(5 terms, 9 symbols) b_counter[4].CLK = b_clk ; "(1 term, 1 symbol) b_counter[4].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[3].T = b_counter[0]*b_counter[1]*b_counter[2] */bwrite_s12 + b_counter[0]*b_counter[1]* b_counter[2]*/reg00 + b_counter[0]*b_counter[1]* b_counter[2]*/wrcontr1 + b_counter[3]*bwrite_s12*/db[3]* reg00*wrcontr1 + /b_counter[3]*bwrite_s12*db[3]* reg00*wrcontr1 ; "(5 terms, 8 symbols) b_counter[3].CLK = b_clk ; "(1 term, 1 symbol) b_counter[3].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[2].T = b_counter[0]*b_counter[1]*/bwrite_s12 + b_counter[0]*b_counter[1]*/reg00 + b_counter[0]*b_counter[1]*/wrcontr1 + b_counter[2]*bwrite_s12*/db[2]* reg00*wrcontr1 + /b_counter[2]*bwrite_s12*db[2]* reg00*wrcontr1 ; "(5 terms, 7 symbols) b_counter[2].CLK = b_clk ; "(1 term, 1 symbol) b_counter[2].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[1].T = b_counter[0]*/bwrite_s12 + b_counter[0]*/reg00 + b_counter[0]*/wrcontr1 + b_counter[1]*bwrite_s12*/db[1]* reg00*wrcontr1 + /b_counter[1]*bwrite_s12*db[1]* reg00*wrcontr1 ; "(5 terms, 6 symbols) b_counter[1].CLK = b_clk ; "(1 term, 1 symbol) b_counter[1].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[0].CLK = b_clk ; "(1 term, 1 symbol) b_counter[0].RESET = noa_rst ; "(1 term, 1 symbol) b_counter[0].T(~) = b_counter[0]*bwrite_s12*db[0]*reg00* wrcontr1 + /b_counter[0]*bwrite_s12*/db[0]* reg00*wrcontr1 ; "(2 terms, 5 symbols) b_clk.EQN = acceptclk[3] + bwrite_s12*/leb2*reg00*wrcontr1 ; "(2 terms, 5 symbols) c_counter[7].T = add_carry-7*/bwrite_s12 + add_carry-7*/reg00 + add_carry-7*/wrcontr1 + bwrite_s12*c_counter[7]*/db[15]* reg00*wrcontr1 + bwrite_s12*/c_counter[7]*db[15]* reg00*wrcontr1 + /bwrite_s12*c_counter[0]* c_counter[1]*/c_counter[2]*c_counter[3]* c_counter[4]*/c_counter[5]*c_counter[6]* c_counter[7] + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7]*/reg00 + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7]* /wrcontr1 ; "(8 terms, 13 symbols) c_counter[7].CLK = c_clk ; "(1 term, 1 symbol) c_counter[7].RESET = noa_rst ; "(1 term, 1 symbol) c_counter[6].T = add_carry-4*/bwrite_s12*c_counter[4]* c_counter[5] + add_carry-4*c_counter[4]* c_counter[5]*/reg00 + add_carry-4*c_counter[4]* c_counter[5]*/wrcontr1 + bwrite_s12*c_counter[6]*/db[14]* reg00*wrcontr1 + bwrite_s12*/c_counter[6]*db[14]* reg00*wrcontr1 + /bwrite_s12*c_counter[0]* c_counter[1]*/c_counter[2]*c_counter[3]* c_counter[4]*/c_counter[5]*c_counter[6]* c_counter[7] + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7]*/reg00 + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7]* /wrcontr1 ; "(8 terms, 13 symbols) c_counter[6].CLK = c_clk ; "(1 term, 1 symbol) c_counter[6].RESET = noa_rst ; "(1 term, 1 symbol) c_counter[5].CLK = c_clk ; "(1 term, 1 symbol) c_counter[5].RESET = noa_rst ; "(1 term, 1 symbol) c_counter[5].T(~) = /add_carry-4*/bwrite_s12 + /add_carry-4*/reg00 + /add_carry-4*/wrcontr1 + bwrite_s12*c_counter[5]*db[13]* reg00*wrcontr1 + bwrite_s12*/c_counter[5]*/db[13]* reg00*wrcontr1 + /bwrite_s12*c_counter[0]* c_counter[1]*/c_counter[2]*c_counter[3]* /c_counter[5]*c_counter[6]*c_counter[7] + /bwrite_s12*/c_counter[4] + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*/c_counter[5]* c_counter[6]*c_counter[7]*/reg00 + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*/c_counter[5]* c_counter[6]*c_counter[7]*/wrcontr1 + /c_counter[4]*/reg00 + /c_counter[4]*/wrcontr1 ; "(11 terms, 13 symbols) c_counter[4].T = add_carry-4*/bwrite_s12 + add_carry-4*/reg00 + add_carry-4*/wrcontr1 + bwrite_s12*c_counter[4]*/db[12]* reg00*wrcontr1 + bwrite_s12*/c_counter[4]*db[12]* reg00*wrcontr1 + /bwrite_s12*c_counter[0]* c_counter[1]*/c_counter[2]*c_counter[3]* c_counter[4]*/c_counter[5]*c_counter[6]* c_counter[7] + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7]*/reg00 + c_counter[0]*c_counter[1]* /c_counter[2]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7]* /wrcontr1 ; "(8 terms, 13 symbols) c_counter[4].CLK = c_clk ; "(1 term, 1 symbol) c_counter[4].RESET = noa_rst ; "(1 term, 1 symbol) c_counter[3].T = bwrite_s12*c_counter[3]*/db[11]*reg00* wrcontr1 + bwrite_s12*/c_counter[3]*db[11]* reg00*wrcontr1 + /bwrite_s12*c_counter[0]* c_counter[1]*c_counter[2] + /bwrite_s12*c_counter[0]* c_counter[1]*c_counter[3]*c_counter[4]* /c_counter[5]*c_counter[6]*c_counter[7] + c_counter[0]*c_counter[1]* c_counter[2]*/reg00 + c_counter[0]*c_counter[1]* c_counter[2]*/wrcontr1 + c_counter[0]*c_counter[1]* c_counter[3]*c_counter[4]*/c_counter[5]* c_counter[6]*c_counter[7]*/reg00 + c_counter[0]*c_counter[1]* c_counter[3]*c_counter[4]*/c_counter[5]* c_counter[6]*c_counter[7]*/wrcontr1 ; "(8 terms, 12 symbols) c_counter[3].CLK = c_clk ; "(1 term, 1 symbol) c_counter[3].RESET = noa_rst ; "(1 term, 1 symbol) c_counter[2].CLK = c_clk ; "(1 term, 1 symbol) c_counter[2].RESET = noa_rst ; "(1 term, 1 symbol) c_counter[2].T(~) = bwrite_s12*c_counter[2]*db[10]*reg00* wrcontr1 + bwrite_s12*/c_counter[2]*/db[10]* reg00*wrcontr1 + /bwrite_s12*/c_counter[0] + /bwrite_s12*/c_counter[1] + /bwrite_s12*/c_counter[2]* c_counter[3]*c_counter[4]*/c_counter[5]* c_counter[6]*c_counter[7] + /c_counter[0]*/reg00 + /c_counter[0]*/wrcontr1 + /c_counter[1]*/reg00 + /c_counter[1]*/wrcontr1 + /c_counter[2]*c_counter[3]* c_counter[4]*/c_counter[5]*c_counter[6]* c_counter[7]*/reg00 + /c_counter[2]*c_counter[3]* c_counter[4]*/c_counter[5]*c_counter[6]* c_counter[7]*/wrcontr1 ; "(11 terms, 12 symbols) c_counter[1].T = bwrite_s12*c_counter[1]*/db[9]*reg00* wrcontr1 + bwrite_s12*/c_counter[1]*db[9]* reg00*wrcontr1 + /bwrite_s12*c_counter[0] + c_counter[0]*/reg00 + c_counter[0]*/wrcontr1 ; "(5 terms, 6 symbols) c_counter[1].CLK = c_clk ; "(1 term, 1 symbol) c_counter[1].RESET = noa_rst ; "(1 term, 1 symbol) c_counter[0].CLK = c_clk ; "(1 term, 1 symbol) c_counter[0].RESET = noa_rst ; "(1 term, 1 symbol) c_counter[0].T(~) = bwrite_s12*c_counter[0]*db[8]*reg00* wrcontr1 + bwrite_s12*/c_counter[0]*/db[8]* reg00*wrcontr1 ; "(2 terms, 5 symbols) c_clk.EQN = bwrite_s12*/leb2*reg00*wrcontr1 + /bwrite_s12*clk_2 + clk_2*/reg00 + clk_2*/wrcontr1 ; "(4 terms, 5 symbols) dboe.EQN(~) = /breadb + /reg00*/reg02*/reg04 ; "(2 terms, 4 symbols) db[15].EQN = reg00*register00[15] + /reg00*reg02*register02c[15] + /reg00*/reg02*register04[15] ; "(3 terms, 5 symbols) db[15].OE = dboe ; "(1 term, 1 symbol) db[14].EQN = reg00*register00[14] + /reg00*reg02*register02c[14] + /reg00*/reg02*register04[14] ; "(3 terms, 5 symbols) db[14].OE = dboe ; "(1 term, 1 symbol) db[13].EQN = reg00*register00[13] + /reg00*reg02*acceptout + /reg00*/reg02*register04[13] ; "(3 terms, 5 symbols) db[13].OE = dboe ; "(1 term, 1 symbol) db[12].EQN = reg00*register00[12] + /reg00*reg02*abortout + /reg00*/reg02*register04[12] ; "(3 terms, 5 symbols) db[12].OE = dboe ; "(1 term, 1 symbol) db[11].EQN = reg00*register00[11] + /reg00*reg02*register02b[11] + /reg00*/reg02*register04[11] ; "(3 terms, 5 symbols) db[11].OE = dboe ; "(1 term, 1 symbol) db[10].EQN = reg00*register00[10] + /reg00*reg02*register02b[10] + /reg00*/reg02*register04[10] ; "(3 terms, 5 symbols) db[10].OE = dboe ; "(1 term, 1 symbol) db[9].EQN = reg00*register00[9] + /reg00*reg02*register02b[9] + /reg00*/reg02*register04[9] ; "(3 terms, 5 symbols) db[9].OE = dboe ; "(1 term, 1 symbol) db[8].EQN = reg00*register00[8] + /reg00*reg02*register02b[8] + /reg00*/reg02*register04[8] ; "(3 terms, 5 symbols) db[8].OE = dboe ; "(1 term, 1 symbol) db[7].EQN = reg00*register00[7] + /reg00*reg02*register02b[7] + /reg00*/reg02*register04[7] ; "(3 terms, 5 symbols) db[7].OE = dboe ; "(1 term, 1 symbol) db[6].EQN = reg00*register00[6] + /reg00*reg02*rosysout_s23[1] + /reg00*/reg02*register04[6] ; "(3 terms, 5 symbols) db[6].OE = dboe ; "(1 term, 1 symbol) db[5].EQN = reg00*register00[5] + /reg00*reg02*rosysout_s23[0] + /reg00*/reg02*t_error ; "(3 terms, 5 symbols) db[5].OE = dboe ; "(1 term, 1 symbol) db[4].EQN = reg00*register00[4] + /reg00*reg02*ttypout[2] + /reg00*/reg02*f_error ; "(3 terms, 5 symbols) db[4].OE = dboe ; "(1 term, 1 symbol) db[3].EQN = reg00*register00[3] + /reg00*reg02*ttypout[1] + /reg00*/reg02*busy ; "(3 terms, 5 symbols) db[3].OE = dboe ; "(1 term, 1 symbol) db[2].EQN = reg00*register00[2] + /reg00*reg02*ttypout[0] + /reg00*/reg02*register04[2] ; "(3 terms, 5 symbols) db[2].OE = dboe ; "(1 term, 1 symbol) db[1].EQN = reg00*register00[1] + /reg00*reg02*testenout + /reg00*/reg02*register04[1] ; "(3 terms, 5 symbols) db[1].OE = dboe ; "(1 term, 1 symbol) db[0].EQN = reg00*register00[0] + /reg00*reg02*register02aa[0] + /reg00*/reg02*register04[0] ; "(3 terms, 5 symbols) db[0].OE = dboe ; "(1 term, 1 symbol) mdb[7].EQN = da[0]*/da[1]*register00[15] + /da[0]*da[1]*register00[7] + /da[0]*/da[1]*register02b[11] ; "(3 terms, 5 symbols) mdb[6].EQN = da[0]*/da[1]*register00[14] + /da[0]*da[1]*register00[6] + /da[0]*/da[1]*register02b[10] ; "(3 terms, 5 symbols) mdb[5].EQN = da[0]*/da[1]*register00[13] + /da[0]*da[1]*register00[5] + /da[0]*/da[1]*register02b[9] ; "(3 terms, 5 symbols) mdb[4].EQN = da[0]*/da[1]*register00[12] + /da[0]*da[1]*register00[4] + /da[0]*/da[1]*register02b[8] ; "(3 terms, 5 symbols) mdb[3].EQN = da[0]*/da[1]*register00[11] + /da[0]*da[1]*register00[3] + /da[0]*/da[1]*register02b[7] ; "(3 terms, 5 symbols) mdb[2].EQN = da[0]*/da[1]*register00[10] + /da[0]*da[1]*register00[2] + /da[0]*/da[1]*rosysout_s23[1] ; "(3 terms, 5 symbols) mdb[1].EQN = da[0]*/da[1]*register00[9] + /da[0]*da[1]*register00[1] + /da[0]*/da[1]*rosysout_s23[0] ; "(3 terms, 5 symbols) mdb[0].EQN = da[0]*/da[1]*register00[8] + /da[0]*da[1]*register00[0] ; "(2 terms, 4 symbols) add_carry-4.EQN = c_counter[0]*c_counter[1]*c_counter[2] *c_counter[3] ; "(1 term, 4 symbols) add_carry-7.EQN = add_carry-4*c_counter[4]*c_counter[5]* c_counter[6] ; "(1 term, 4 symbols) add_carry-13.EQN = b_counter[0]*b_counter[1]*b_counter[2] *b_counter[3]*b_counter[4] ; "(1 term, 5 symbols) PLDocument: Y:\clock\zeus\master\pld2\pld2.doc SOLUTIONS Tue Feb 29 14:58:16 2000 PARTITIONING CRITERIA : WEIGHT PRICE 10 ; TEMPLATE = M4-32/32 OR M4-256/128; PARTITIONING SOLUTIONS : ==> Solution 1: MV512_184 FUSEMAP FILES FOR SOLUTION 1: Device 1 (MV512_184) : Y:\clock\zeus\master\pld2\pld2.j1 PLDocument: Y:\clock\zeus\master\pld2\pld2.doc PINOUT DIAGRAMS Tue Feb 29 14:58:16 2000 Device 1 - MV512_184 -- Pinout for QFP package +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 1 |Jtag | | | 51 |Vcc | | | 2 |Biput | fltn[0] | | 52 |Biput | mdb[0] | | 3 |Biput | fltn[1] | | 53 |Biput | mdb[1] | | 4 |Biput | fltn[2] | | 54 |Biput | mdb[2] | | 5 |Biput | fltn[3] | | 55 |Biput | mdb[3] | | 6 |Biput | fltn[4] | | 56 |Biput | mdb[4] | | 7 |Biput | fltn[5] | | 57 |Biput | mdb[5] | | 8 |Biput | fltn[6] | | 58 |Biput | mdb[6] | | 9 |Biput | fltn[7] | | 59 |Biput | mdb[7] | | 10 |Vcc | | | 60 |Jtag | | | 11 |GND | | | 61 |GND | | | 12 |Biput | gbcn[0] | | 62 |Vcc | | | 13 |Biput | gbcn[1] | | 63 |Biput | db[0] | | 14 |Biput | gbcn[2] | | 64 |Biput | db[1] | | 15 |Biput | gbcn[3] | | 65 |Biput | db[2] | | 16 |Biput | gbcn[4] | | 66 |Biput | db[3] | | 17 |Biput | gbcn[5] | | 67 |Biput | db[4] | | 18 |Biput | gbcn[6] | | 68 |Biput | db[5] | | 19 |Biput | gbcn[7] | | 69 |Biput | db[6] | | 20 |GND | | | 70 |Biput | db[7] | | 21 |Biput | | | 71 |GND | | | 22 |Biput | clk_2 | | 72 |Vcc | | | 23 |Biput | | | 73 |Biput | db[8] | | 24 |Biput | | | 74 |Biput | db[9] | | 25 |Biput | acceptclk[3] | | 75 |Biput | db[10] | | 26 |Biput | | | 76 |Biput | db[11] | | 27 |Biput | | | 77 |Biput | db[12] | | 28 |Biput | | | 78 |Biput | db[13] | | 29 |In/CLK| clk_1 | | 79 |Biput | db[14] | | 30 |Vcc | | | 80 |Biput | db[15] | | 31 |GND | | | 81 |GND | | | 32 |In/CLK| clk_3 | | 82 |Biput | | | 33 |Biput | reg00 | | 83 |Biput | | | 34 |Biput | reg02 | | 84 |Biput | | | 35 |Biput | reg04 | | 85 |Biput | | | 36 |Biput | | | 86 |Biput | | | 37 |Biput | da[0] | | 87 |Biput | | | 38 |Biput | da[1] | | 88 |Vcc | | | 39 |Biput | | | 89 |GND | | | 40 |Biput | | | 90 |GND | | | 41 |GND | | | 91 |GND | | | 42 |Biput | | | 92 |GND | | | 43 |Biput | | | 93 |Vcc | | | 44 |Biput | | | 94 |Biput | | | 45 |Biput | | | 95 |Biput | | | 46 |Biput | | | 96 |Biput | | | 47 |Biput | | | 97 |Biput | | | 48 |Biput | | | 98 |Biput | | | 49 |Biput | | | 99 |Biput | | | 50 |GND | | | 100 |GND | | +-------+------+----------------------+ +-------+------+----------------------+ Device 1 - MV512_184 -- Pinout for QFP package (continued) +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 101 |Biput | testen | | 151 |GND | | | 102 |Biput | ttyp[0] | | 152 |In/CLK| testenclk1 | | 103 |Biput | ttyp[1] | | 153 |Biput | empty_g[0] | | 104 |Biput | ttyp[2] | | 154 |Biput | empty_g[1] | | 105 |Biput | rosys[0] | | 155 |Biput | empty_g[2] | | 106 |Biput | rosys[1] | | 156 |Biput | empty_g[3] | | 107 |Biput | roamb[0] | | 157 |Biput | empty_g[4] | | 108 |Biput | roamb[1] | | 158 |Biput | empty_g[5] | | 109 |Vcc | | | 159 |Biput | empty_g[6] | | 110 |GND | | | 160 |Biput | empty_g[7] | | 111 |Biput | rousr[0] | | 161 |GND | | | 112 |Biput | rousr[1] | | 162 |Biput | empty_g[8] | | 113 |Biput | rousr[2] | | 163 |Biput | bplane_empty | | 114 |Biput | gfltabort | | 164 |Biput | bplane_busy | | 115 |Biput | gfltaccept | | 165 |Biput | bplane_f_error | | 116 |Biput | | | 166 |Biput | bplane_error | | 117 |Biput | | | 167 |Biput | bplane_reset | | 118 |Biput | | | 168 |Biput | bplane_abort | | 119 |Vcc | | | 169 |Biput | bplane_accept | | 120 |GND | | | 170 |GND | | | 121 |Jtag | | | 171 |Vcc | | | 122 |Biput | testenout | | 172 |Biput | breadb | | 123 |Biput | ttypout[0] | | 173 |Biput | bwriteb | | 124 |Biput | ttypout[1] | | 174 |Biput | leb2 | | 125 |Biput | ttypout[2] | | 175 |Biput | noa_rst | | 126 |Biput | abortout | | 176 |Biput | | | 127 |Biput | acceptout | | 177 |Biput | wrcontr1 | | 128 |Biput | | | 178 |Biput | | | 129 |Biput | | | 179 |Biput | | | 130 |Vcc | | | 180 |Jtag | | | 131 |GND | | | 181 |GND | | | 132 |Biput | busyout | | 182 |Vcc | | | 133 |Biput | f_errorout | | 183 |Biput | | | 134 |Biput | t_errorout | | 184 |Biput | | | 135 |Biput | busy | | 185 |Biput | | | 136 |Biput | f_error | | 186 |Biput | | | 137 |Biput | t_error | | 187 |Biput | | | 138 |Biput | | | 188 |Biput | | | 139 |Biput | | | 189 |Biput | | | 140 |GND | | | 190 |Biput | | | 141 |Biput | | | 191 |GND | | | 142 |Biput | | | 192 |Vcc | | | 143 |Biput | | | 193 |Biput | | | 144 |Biput | | | 194 |Biput | | | 145 |Biput | | | 195 |Biput | | | 146 |Biput | | | 196 |Biput | | | 147 |Biput | | | 197 |Biput | | | 148 |Biput | | | 198 |Biput | | | 149 |In/CLK| acceptclk[1] | | 199 |Biput | | | 150 |Vcc | | | 200 |Biput | | +-------+------+----------------------+ +-------+------+----------------------+ Device 1 - MV512_184 -- Pinout for QFP package (continued) +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 201 |GND | | | 221 |Biput | s12[0] | | 202 |Biput | | | 222 |Biput | s12[1] | | 203 |Biput | | | 223 |Biput | s12[2] | | 204 |Biput | | | 224 |Biput | bwrite_s12 | | 205 |Biput | | | 225 |Biput | s23[0] | | 206 |Biput | | | 226 |Biput | s23[1] | | 207 |Biput | | | 227 |Biput | rosysout_s23[0] | | 208 |Vcc | | | 228 |Biput | rosysout_s23[1] | | 209 |GND | | | 229 |Vcc | | | 210 |GND | | | 230 |GND | | | 211 |GND | | | 231 |Biput | | | 212 |GND | | | 232 |Biput | ttypout_s24[0] | | 213 |Vcc | | | 233 |Biput | ttypout_s24[1] | | 214 |Biput | | | 234 |Biput | ttypout_s24[2] | | 215 |Biput | | | 235 |Biput | | | 216 |Biput | | | 236 |Biput | | | 217 |Biput | | | 237 |Biput | local_bcn0_s24 | | 218 |Biput | | | 238 |Biput | | | 219 |Biput | | | 239 |Vcc | | | 220 |GND | | | 240 |GND | | +-------+------+----------------------+ +-------+------+----------------------+ DEVICE SELECTION: Device Man Fam Pack Temp ICC TPD Fmax Price User ==> M5-512/184-7HC AMD CMOS QFP COM 999.9ma 9.5ns 105.0MHz $ 0.00 0 0 PLDocument: Y:\clock\zeus\master\pld2\pld2.doc WIRELIST Tue Feb 29 14:58:16 2000 +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | noa_rst | MV512_184_1 | 175 | | bwrite_s12 | MV512_184_1 | 224 | | bwriteb | MV512_184_1 | 173 | | breadb | MV512_184_1 | 172 | | reg00 | MV512_184_1 | 33 | | reg02 | MV512_184_1 | 34 | | reg04 | MV512_184_1 | 35 | | leb2 | MV512_184_1 | 174 | | clk_1 | MV512_184_1 | 29 | | clk_2 | MV512_184_1 | 22 | | clk_3 | MV512_184_1 | 32 | | da[1] | MV512_184_1 | 38 | | da[0] | MV512_184_1 | 37 | | acceptclk[3] | MV512_184_1 | 25 | | acceptclk[1] | MV512_184_1 | 149 | | testenclk1 | MV512_184_1 | 152 | | wrcontr1 | MV512_184_1 | 177 | | empty_g[8] | MV512_184_1 | 162 | | empty_g[7] | MV512_184_1 | 160 | | empty_g[6] | MV512_184_1 | 159 | | empty_g[5] | MV512_184_1 | 158 | | empty_g[4] | MV512_184_1 | 157 | | empty_g[3] | MV512_184_1 | 156 | | empty_g[2] | MV512_184_1 | 155 | | empty_g[1] | MV512_184_1 | 154 | | empty_g[0] | MV512_184_1 | 153 | | fltn[7] | MV512_184_1 | 9 | | fltn[6] | MV512_184_1 | 8 | | fltn[5] | MV512_184_1 | 7 | | fltn[4] | MV512_184_1 | 6 | | fltn[3] | MV512_184_1 | 5 | | fltn[2] | MV512_184_1 | 4 | | fltn[1] | MV512_184_1 | 3 | | fltn[0] | MV512_184_1 | 2 | | gbcn[7] | MV512_184_1 | 19 | | gbcn[6] | MV512_184_1 | 18 | | gbcn[5] | MV512_184_1 | 17 | | gbcn[4] | MV512_184_1 | 16 | | gbcn[3] | MV512_184_1 | 15 | | gbcn[2] | MV512_184_1 | 14 | | gbcn[1] | MV512_184_1 | 13 | | gbcn[0] | MV512_184_1 | 12 | | testen | MV512_184_1 | 101 | | ttyp[2] | MV512_184_1 | 104 | | ttyp[1] | MV512_184_1 | 103 | | ttyp[0] | MV512_184_1 | 102 | | rosys[1] | MV512_184_1 | 106 | | rosys[0] | MV512_184_1 | 105 | | roamb[1] | MV512_184_1 | 108 | | roamb[0] | MV512_184_1 | 107 | | rousr[2] | MV512_184_1 | 113 | +------------------+-------------------+-------+ +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | rousr[1] | MV512_184_1 | 112 | | rousr[0] | MV512_184_1 | 111 | | gfltabort | MV512_184_1 | 114 | | gfltaccept | MV512_184_1 | 115 | | acceptout | MV512_184_1 | 127 | | abortout | MV512_184_1 | 126 | | rosysout_s23[1] | MV512_184_1 | 228 | | rosysout_s23[0] | MV512_184_1 | 227 | | ttypout[2] | MV512_184_1 | 125 | | ttypout[1] | MV512_184_1 | 124 | | ttypout[0] | MV512_184_1 | 123 | | testenout | MV512_184_1 | 122 | | ttypout_s24[2] | MV512_184_1 | 234 | | ttypout_s24[1] | MV512_184_1 | 233 | | ttypout_s24[0] | MV512_184_1 | 232 | | local_bcn0_s24 | MV512_184_1 | 237 | | busyout | MV512_184_1 | 132 | | f_errorout | MV512_184_1 | 133 | | t_errorout | MV512_184_1 | 134 | | bplane_accept | MV512_184_1 | 169 | | bplane_abort | MV512_184_1 | 168 | | bplane_reset | MV512_184_1 | 167 | | bplane_error | MV512_184_1 | 166 | | bplane_f_error | MV512_184_1 | 165 | | bplane_busy | MV512_184_1 | 164 | | bplane_empty | MV512_184_1 | 163 | | t_error | MV512_184_1 | 137 | | f_error | MV512_184_1 | 136 | | busy | MV512_184_1 | 135 | | db[15] | MV512_184_1 | 80 | | db[14] | MV512_184_1 | 79 | | db[13] | MV512_184_1 | 78 | | db[12] | MV512_184_1 | 77 | | db[11] | MV512_184_1 | 76 | | db[10] | MV512_184_1 | 75 | | db[9] | MV512_184_1 | 74 | | db[8] | MV512_184_1 | 73 | | db[7] | MV512_184_1 | 70 | | db[6] | MV512_184_1 | 69 | | db[5] | MV512_184_1 | 68 | | db[4] | MV512_184_1 | 67 | | db[3] | MV512_184_1 | 66 | | db[2] | MV512_184_1 | 65 | | db[1] | MV512_184_1 | 64 | | db[0] | MV512_184_1 | 63 | | mdb[7] | MV512_184_1 | 59 | | mdb[6] | MV512_184_1 | 58 | | mdb[5] | MV512_184_1 | 57 | | mdb[4] | MV512_184_1 | 56 | | mdb[3] | MV512_184_1 | 55 | | mdb[2] | MV512_184_1 | 54 | +------------------+-------------------+-------+ +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | mdb[1] | MV512_184_1 | 53 | | mdb[0] | MV512_184_1 | 52 | | s12[2] | MV512_184_1 | 223 | | s12[1] | MV512_184_1 | 222 | | s12[0] | MV512_184_1 | 221 | | s23[1] | MV512_184_1 | 226 | | s23[0] | MV512_184_1 | 225 | +------------------+-------------------+-------+