"===================================================================================================
#TITLE    'C&C, VME INTERFACE';
#ENGINEER 'Dominic A Hayes';
#COMPANY  'University College London';
#COMMENT  'A32/A24 VME interface';
"===================================================================================================
"
"                 D16:A24/A32 VME SLAVE interface.
"
"          ***   USES EXTERNAL VME DATA LATCHES (74ALS543)  ***
"
"MODIFIED
"15NOV99 2nd bwrite o/p (bwrite_s12) o/p on spare line to PLD2 (then PLD3).
"===================================================================================================
"                                        SIGNAL DECLARATIONS
"===================================================================================================

LOW_TRUE INPUT  lwordb;                   "Buffered VME signal.
LOW_TRUE INPUT  writeb;                   "Buffered VME Data Write.
LOW_TRUE INPUT  berrb;                    "Buffered VME Bus ERRor.
LOW_TRUE INPUT  ds0b, ds1b;               "Buffered VME Data Strobes.
LOW_TRUE INPUT  iackb;                    "Buffered VME Interupt ACKnowledge.
         INPUT  amb[5..0];                "Buffered VME Address Modifier.
         INPUT  ab[31..1];                "Buffered VME Address bus.
         INPUT  dl1;                      "delayed Data Strobe.
         INPUT  dl2;                      "delayed Data Strobe.
         INPUT  dl3;                      "delayed Data Strobe.
         INPUT  base_addr[31..16];        "selected base address from DIP(SY) switch (16bit address).
         INPUT  a32_mode;                 "address mode select, A32 (HIGH) or A24 (LOW).

         NODE   ds;                       " - "OR'ed" ds0/1b.
         NODE   ssda, snda, esda, enda    "Address modifier codes.
                   DEFAULT_TO 0;
         NODE   am_OK                     "Correct Address Modifier for boabread.
                   CLOCKED_BY dl1
                   RESET_BY /ds;          "Falling edge of ds (cycle finished).
         NODE   addr_OK                   "VME address = base address.
                   CLOCKED_BY dl1
                   RESET_BY /ds
                   DEFAULT_TO 0;
         NODE   a[15..1]                  "ab[15..1] Latched.
                   CLOCKED_BY dl1
                   RESET_BY /ds;
         NODE   bdsel;                    "BoarD SELect.

         OUTPUT dl0;                      " "OR'ed" ds0/1b, Data Strobe, to delay line.
         OUTPUT ack;                      "Data Transfer ACK (to external OC device).
         OUTPUT reg[4]                    "Register addressed encoded onto 4 bits.
                   DEFAULT_TO 0;
LOW_TRUE OUTPUT reg00, reg02, reg04, reg06, reg08, reg0A, reg0C, reg0E,
                reg10, reg12, reg14, reg16, reg18, reg1A, reg1C, reg1E
                  DEFAULT_TO 0;
LOW_TRUE OUTPUT oein, oeout;              "Output Enables for vme data bus '543 latches.
LOW_TRUE OUTPUT le1;                      " '543 vme data latches enable (/LEAB = /LEBA).
LOW_TRUE OUTPUT nle1;                     "inverted le1.
LOW_TRUE OUTPUT le2;                      " '996 registers clock.
LOW_TRUE OUTPUT load;                     "
LOW_TRUE OUTPUT errorled;                 "Bus ERRor when board addressed.
LOW_TRUE OUTPUT bwrite;                   "Writeb to '543 vme d[15..0] latches.
LOW_TRUE OUTPUT bread;                    "ReaD signal to '543 vme bus d[15..0] latches
                                          "   & '996 addressed db[15..0] registers.
LOW_TRUE OUTPUT bwrite_s12;               "2nd bwrite fed to PLD2 (and then PLD3) via spare o/i pin.


"SPARE I/O
"---------
         INPUT    s12[3];        "spare outputs.  was 4, one taken by bwrite_sp.
         INPUT    s13[4];        "spare outputs.
         INPUT    s14[4];        "spare outputs.


"===================================================================================================
"                                            EQUATIONS
"===================================================================================================
ds     = ds0b + ds1b;          " - OR'ed  Data Strobes
dl0    = ds;

a[15..1]   = ab[15..1];        "Latched low address signals.
bwrite     =  writeb;          "original bwrite signal.
bwrite_s12 =  writeb;          "2nd bwrite signal
bread      = /writeb;          "

IF (/iackb * /lwordb) THEN     "ADDRESS MODIFIER DECODE
   CASE amb                    "=======================
      WHEN 3Dh => ssda = 1;    "Standard supervisory data access.
      WHEN 39h => snda = 1;    "Standard non-privaleged data access.
      WHEN 0Dh => esda = 1;    "Extended supervisory data access.
      WHEN 09h => enda = 1;    "Extended non-privaleged data access.
   END CASE;
END IF;

IF a32_mode THEN                             "A32 MODE.
   am_OK = ssda + snda + esda + enda;        "Any of the A24/A32 data access codes.
   IF (ab[31..16] = base_addr[31..16]) THEN  "VME address matches board address.
      addr_OK = 1;
   END IF;
ELSE                                         "A24 MODE.
   am_OK = ssda + snda;                      "Either of the A24 data access codes.
   IF (ab[23..16] = base_addr[23..16]) THEN  "VME address matches board address.
      addr_OK = 1;
   END IF;
END IF;

bdsel   = am_OK * addr_OK;                   "BoarD SELected when both asserted.

IF bdsel THEN                                "REGISTER ADDRESS DECODE
   reg = a[4..1];                            " Register address encoded into 4 bits
   CASE a
      WHEN 0  => reg00 = 1;         "=======================
      WHEN 1  => reg02 = 1;         "REGISTER ADDRESS DECODE
      WHEN 2  => reg04 = 1;         "=======================
      WHEN 3  => reg06 = 1;
      WHEN 4  => reg08 = 1;         "NB a[0] not used.
      WHEN 5  => reg0A = 1;
      WHEN 6  => reg0C = 1;
      WHEN 7  => reg0E = 1;
      WHEN 8  => reg10 = 1;
      WHEN 9  => reg12 = 1;
      WHEN 10 => reg14 = 1;
      WHEN 11 => reg16 = 1;
      WHEN 12 => reg18 = 1;
      WHEN 13 => reg1A = 1;
      WHEN 14 => reg1C = 1;
      WHEN 15 => reg1E = 1;
   END CASE;
END IF;

le1      = bdsel * /dl2;
nle1     = /le1;
le2      = le1   * bwrite;
load     = dl3   * bwrite;
oein     = bdsel * bwrite;
oeout    = bdsel * bread * dl2;
errorled = berrb * addr_OK;

ack      = bdsel AND dl2;
"==================================================================================================