PLDocument: Y:\clock\zeus\master\pld1\pld1.doc TITLE PAGE Mon Nov 15 18:17:13 1999 R MACHXL6.2.0.18 - (c) Copyright MINC Incorporated 1987-1998 ============================================================================== TITLE : C&C, VME INTERFACE FILE : Y:\clock\zeus\master\pld1\pld1 DATE : Mon Nov 15 18:17:13 1999 ENGINEER : Dominic A Hayes COMPANY : University College London COMMENTS : A32/A24 VME interface ============================================================================== MODULES : Document Generator 3.69 File Handler 6.2 Language Compiler 3.83 Architectural Optimizer 3.110 Device Lib Scan 3.2 Device Library 3.1 Device Partition 3.14 Device Fusemap 3.88 SWITCH VALUES : (Value in parenthesis represents batch mode switch value) PLCOMP PRODUCT TERM LIMIT : 128 PLOPT PRODUCT TERM LIMIT : 128 PLOPT REDUCTION : Espresso (1) NODE GENERATION : Procedure Instantiation Arithmetic and Relational Operators (1) PLDocument: Y:\clock\zeus\master\pld1\pld1.doc EQUATIONS Mon Nov 15 18:17:13 1999 EQUATIONS FOR SYSTEM INPUT SIGNALS (74) : LOW_TRUE lwordb LOW_TRUE writeb LOW_TRUE berrb LOW_TRUE ds0b LOW_TRUE ds1b LOW_TRUE iackb amb[5..0] ab[31..1] dl1 dl2 dl3 base_addr[31..16] a32_mode s12[2..0] s13[3..0] s14[3..0] OUTPUT SIGNALS (32) : dl0 ack reg[3..0] LOW_TRUE reg00 LOW_TRUE reg02 LOW_TRUE reg04 LOW_TRUE reg06 LOW_TRUE reg08 LOW_TRUE reg0A LOW_TRUE reg0C LOW_TRUE reg0E LOW_TRUE reg10 LOW_TRUE reg12 LOW_TRUE reg14 LOW_TRUE reg16 LOW_TRUE reg18 LOW_TRUE reg1A LOW_TRUE reg1C LOW_TRUE reg1E LOW_TRUE oein LOW_TRUE oeout LOW_TRUE le1 LOW_TRUE nle1 LOW_TRUE le2 LOW_TRUE load LOW_TRUE errorled LOW_TRUE bwrite LOW_TRUE bread LOW_TRUE bwrite_s12 PHYSICAL NODE SIGNALS (20) : am_OK addr_OK a[15..1] equal_to-7 equal_to-14 equal_to-22 REDUCED EQUATIONS: dl0.EQN(~) = /ds0b*/ds1b ; "(1 term, 2 symbols) am_OK.D = a32_mode*amb[0]*/amb[1]*amb[3]*/amb[4] */amb[5]*/iackb*/lwordb + amb[0]*/amb[1]*amb[3]*amb[4]*amb[5] */iackb*/lwordb ; "(2 terms, 8 symbols) am_OK.CLK = dl1 ; "(1 term, 1 symbol) am_OK.RESET = /dl0 ; "(1 term, 1 symbol) addr_OK.D = a32_mode*/equal_to-14*/equal_to-7 + /a32_mode*/equal_to-22 ; "(2 terms, 4 symbols) addr_OK.CLK = dl1 ; "(1 term, 1 symbol) addr_OK.RESET = /dl0 ; "(1 term, 1 symbol) a[15].D = ab[15] ; "(1 term, 1 symbol) a[15].CLK = dl1 ; "(1 term, 1 symbol) a[15].RESET = /dl0 ; "(1 term, 1 symbol) a[14].D = ab[14] ; "(1 term, 1 symbol) a[14].CLK = dl1 ; "(1 term, 1 symbol) a[14].RESET = /dl0 ; "(1 term, 1 symbol) a[13].D = ab[13] ; "(1 term, 1 symbol) a[13].CLK = dl1 ; "(1 term, 1 symbol) a[13].RESET = /dl0 ; "(1 term, 1 symbol) a[12].D = ab[12] ; "(1 term, 1 symbol) a[12].CLK = dl1 ; "(1 term, 1 symbol) a[12].RESET = /dl0 ; "(1 term, 1 symbol) a[11].D = ab[11] ; "(1 term, 1 symbol) a[11].CLK = dl1 ; "(1 term, 1 symbol) a[11].RESET = /dl0 ; "(1 term, 1 symbol) a[10].D = ab[10] ; "(1 term, 1 symbol) a[10].CLK = dl1 ; "(1 term, 1 symbol) a[10].RESET = /dl0 ; "(1 term, 1 symbol) a[9].D = ab[9] ; "(1 term, 1 symbol) a[9].CLK = dl1 ; "(1 term, 1 symbol) a[9].RESET = /dl0 ; "(1 term, 1 symbol) a[8].D = ab[8] ; "(1 term, 1 symbol) a[8].CLK = dl1 ; "(1 term, 1 symbol) a[8].RESET = /dl0 ; "(1 term, 1 symbol) a[7].D = ab[7] ; "(1 term, 1 symbol) a[7].CLK = dl1 ; "(1 term, 1 symbol) a[7].RESET = /dl0 ; "(1 term, 1 symbol) a[6].D = ab[6] ; "(1 term, 1 symbol) a[6].CLK = dl1 ; "(1 term, 1 symbol) a[6].RESET = /dl0 ; "(1 term, 1 symbol) a[5].D = ab[5] ; "(1 term, 1 symbol) a[5].CLK = dl1 ; "(1 term, 1 symbol) a[5].RESET = /dl0 ; "(1 term, 1 symbol) a[4].D = ab[4] ; "(1 term, 1 symbol) a[4].CLK = dl1 ; "(1 term, 1 symbol) a[4].RESET = /dl0 ; "(1 term, 1 symbol) a[3].D = ab[3] ; "(1 term, 1 symbol) a[3].CLK = dl1 ; "(1 term, 1 symbol) a[3].RESET = /dl0 ; "(1 term, 1 symbol) a[2].D = ab[2] ; "(1 term, 1 symbol) a[2].CLK = dl1 ; "(1 term, 1 symbol) a[2].RESET = /dl0 ; "(1 term, 1 symbol) a[1].D = ab[1] ; "(1 term, 1 symbol) a[1].CLK = dl1 ; "(1 term, 1 symbol) a[1].RESET = /dl0 ; "(1 term, 1 symbol) ack.EQN = dl2*oein + oeout ; "(2 terms, 3 symbols) reg[3].EQN = a[4]*addr_OK*am_OK ; "(1 term, 3 symbols) reg[2].EQN = a[3]*addr_OK*am_OK ; "(1 term, 3 symbols) reg[1].EQN = a[2]*addr_OK*am_OK ; "(1 term, 3 symbols) reg[0].EQN = a[1]*addr_OK*am_OK ; "(1 term, 3 symbols) reg00.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*/a[1]*/a[2]*/a[3]*/a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg02.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*a[1]*/a[2]*/a[3]*/a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg04.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*/a[1]*a[2]*/a[3]*/a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg06.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*a[1]*a[2]*/a[3]*/a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg08.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*/a[1]*/a[2]*a[3]*/a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg0A.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*a[1]*/a[2]*a[3]*/a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg0C.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*/a[1]*a[2]*a[3]*/a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg0E.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*a[1]*a[2]*a[3]*/a[4]*/a[5]*/a[6] */a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg10.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*/a[1]*/a[2]*/a[3]*a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg12.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*a[1]*/a[2]*/a[3]*a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg14.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*/a[1]*a[2]*/a[3]*a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg16.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*a[1]*a[2]*/a[3]*a[4]*/a[5]*/a[6] */a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg18.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*/a[1]*/a[2]*a[3]*a[4]*/a[5]* /a[6]*/a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg1A.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*a[1]*/a[2]*a[3]*a[4]*/a[5]*/a[6] */a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg1C.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*/a[1]*a[2]*a[3]*a[4]*/a[5]*/a[6] */a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) reg1E.EQN = /a[10]*/a[11]*/a[12]*/a[13]*/a[14]* /a[15]*a[1]*a[2]*a[3]*a[4]*/a[5]*/a[6]* /a[7]*/a[8]*/a[9]*addr_OK*am_OK ; "(1 term, 17 symbols) oein.EQN = addr_OK*am_OK*bwrite ; "(1 term, 3 symbols) oeout.EQN = addr_OK*am_OK*bread*dl2 ; "(1 term, 4 symbols) le1.EQN = addr_OK*am_OK*/dl2 ; "(1 term, 3 symbols) nle1.EQN = /le1 ; "(1 term, 1 symbol) le2.EQN = bwrite*le1 ; "(1 term, 2 symbols) load.EQN = bwrite*dl3 ; "(1 term, 2 symbols) errorled.EQN = addr_OK*berrb ; "(1 term, 2 symbols) bwrite.EQN = writeb ; "(1 term, 1 symbol) bread.EQN = /writeb ; "(1 term, 1 symbol) bwrite_s12.EQN = writeb ; "(1 term, 1 symbol) equal_to-7.EQN = ab[16]*/base_addr[16] + /ab[16]*base_addr[16] + ab[17]*/base_addr[17] + /ab[17]*base_addr[17] + ab[18]*/base_addr[18] + /ab[18]*base_addr[18] + ab[19]*/base_addr[19] + /ab[19]*base_addr[19] + ab[20]*/base_addr[20] + /ab[20]*base_addr[20] + ab[21]*/base_addr[21] + /ab[21]*base_addr[21] + ab[22]*/base_addr[22] + /ab[22]*base_addr[22] + ab[23]*/base_addr[23] + /ab[23]*base_addr[23] ; "(16 terms, 16 symbols) equal_to-14.EQN = ab[24]*/base_addr[24] + /ab[24]*base_addr[24] + ab[25]*/base_addr[25] + /ab[25]*base_addr[25] + ab[26]*/base_addr[26] + /ab[26]*base_addr[26] + ab[27]*/base_addr[27] + /ab[27]*base_addr[27] + ab[28]*/base_addr[28] + /ab[28]*base_addr[28] + ab[29]*/base_addr[29] + /ab[29]*base_addr[29] + ab[30]*/base_addr[30] + /ab[30]*base_addr[30] + ab[31]*/base_addr[31] + /ab[31]*base_addr[31] ; "(16 terms, 16 symbols) equal_to-22.EQN = ab[16]*/base_addr[16] + /ab[16]*base_addr[16] + ab[17]*/base_addr[17] + /ab[17]*base_addr[17] + ab[18]*/base_addr[18] + /ab[18]*base_addr[18] + ab[19]*/base_addr[19] + /ab[19]*base_addr[19] + ab[20]*/base_addr[20] + /ab[20]*base_addr[20] + ab[21]*/base_addr[21] + /ab[21]*base_addr[21] + ab[22]*/base_addr[22] + /ab[22]*base_addr[22] + ab[23]*/base_addr[23] + /ab[23]*base_addr[23] ; "(16 terms, 16 symbols) PLDocument: Y:\clock\zeus\master\pld1\pld1.doc SOLUTIONS Mon Nov 15 18:17:13 1999 PARTITIONING CRITERIA : WEIGHT PRICE 10 ; TEMPLATE = MV128_120 ; PARTITIONING SOLUTIONS : ==> Solution 1: MV128_120 FUSEMAP FILES FOR SOLUTION 1: Device 1 (MV128_120) : Y:\clock\zeus\master\pld1\pld1.j1 PLDocument: Y:\clock\zeus\master\pld1\pld1.doc PINOUT DIAGRAMS Mon Nov 15 18:17:13 1999 Device 1 - MV128_120 -- Pinout for QFP package +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 1 |Jtag | | | 51 |GND | | | 2 |Biput | reg10 | | 52 |Vcc | | | 3 |Biput | reg12 | | 53 |Biput | s12[0] | | 4 |Biput | reg14 | | 54 |Biput | s12[1] | | 5 |Biput | reg16 | | 55 |Biput | s12[2] | | 6 |Biput | reg18 | | 56 |Biput | bwrite_s12 | | 7 |Biput | reg1A | | 57 |Biput | s13[0] | | 8 |Biput | reg1C | | 58 |Biput | s13[1] | | 9 |Biput | reg1E | | 59 |Vcc | | | 10 |GND | | | 60 |GND | | | 11 |Biput | base_addr[16] | | 61 |GND | | | 12 |Biput | base_addr[17] | | 62 |Vcc | | | 13 |Biput | base_addr[18] | | 63 |Biput | amb[0] | | 14 |Biput | base_addr[19] | | 64 |Biput | amb[1] | | 15 |Biput | base_addr[20] | | 65 |Biput | amb[2] | | 16 |Biput | base_addr[21] | | 66 |Biput | amb[3] | | 17 |Biput | base_addr[22] | | 67 |Biput | amb[4] | | 18 |Biput | base_addr[23] | | 68 |Biput | amb[5] | | 19 |In/CLK| | | 69 |Vcc | | | 20 |Vcc | | | 70 |GND | | | 21 |GND | | | 71 |Biput | ab[24] | | 22 |In/CLK| | | 72 |Biput | ab[25] | | 23 |Biput | base_addr[24] | | 73 |Biput | ab[26] | | 24 |Biput | base_addr[25] | | 74 |Biput | ab[27] | | 25 |Biput | base_addr[26] | | 75 |Biput | ab[28] | | 26 |Biput | base_addr[27] | | 76 |Biput | ab[29] | | 27 |Biput | base_addr[28] | | 77 |Biput | ab[30] | | 28 |Biput | base_addr[29] | | 78 |Biput | ab[31] | | 29 |Biput | base_addr[30] | | 79 |Vcc | | | 30 |Biput | base_addr[31] | | 80 |GND | | | 31 |GND | | | 81 |Jtag | | | 32 |Biput | dl0 | | 82 |Biput | | | 33 |Biput | dl1 | | 83 |Biput | ab[1] | | 34 |Biput | dl2 | | 84 |Biput | ab[2] | | 35 |Biput | dl3 | | 85 |Biput | ab[3] | | 36 |Biput | | | 86 |Biput | ab[4] | | 37 |Biput | | | 87 |Biput | ab[5] | | 38 |Biput | errorled | | 88 |Biput | ab[6] | | 39 |Biput | ack | | 89 |Biput | ab[7] | | 40 |Jtag | | | 90 |GND | | | 41 |GND | | | 91 |Biput | ab[8] | | 42 |Vcc | | | 92 |Biput | ab[9] | | 43 |Biput | reg[0] | | 93 |Biput | ab[10] | | 44 |Biput | reg[1] | | 94 |Biput | ab[11] | | 45 |Biput | reg[2] | | 95 |Biput | ab[12] | | 46 |Biput | reg[3] | | 96 |Biput | ab[13] | | 47 |Biput | | | 97 |Biput | ab[14] | | 48 |Biput | | | 98 |Biput | ab[15] | | 49 |Biput | | | 99 |In/CLK| | | 50 |Biput | | | 100 |Vcc | | +-------+------+----------------------+ +-------+------+----------------------+ Device 1 - MV128_120 -- Pinout for QFP package (continued) +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 101 |GND | | | 131 |GND | | | 102 |In/CLK| | | 132 |Vcc | | | 103 |Biput | ab[16] | | 133 |Biput | oein | | 104 |Biput | ab[17] | | 134 |Biput | oeout | | 105 |Biput | ab[18] | | 135 |Biput | le1 | | 106 |Biput | ab[19] | | 136 |Biput | nle1 | | 107 |Biput | ab[20] | | 137 |Biput | le2 | | 108 |Biput | ab[21] | | 138 |Biput | load | | 109 |Biput | ab[22] | | 139 |Vcc | | | 110 |Biput | ab[23] | | 140 |GND | | | 111 |GND | | | 141 |GND | | | 112 |Biput | iackb | | 142 |Vcc | | | 113 |Biput | lwordb | | 143 |Biput | bwrite | | 114 |Biput | writeb | | 144 |Biput | bread | | 115 |Biput | berrb | | 145 |Biput | | | 116 |Biput | | | 146 |Biput | | | 117 |Biput | | | 147 |Biput | | | 118 |Biput | ds0b | | 148 |Biput | | | 119 |Biput | ds1b | | 149 |Vcc | | | 120 |Jtag | | | 150 |GND | | | 121 |GND | | | 151 |Biput | reg00 | | 122 |Vcc | | | 152 |Biput | reg02 | | 123 |Biput | s13[2] | | 153 |Biput | reg04 | | 124 |Biput | s13[3] | | 154 |Biput | reg06 | | 125 |Biput | s14[0] | | 155 |Biput | reg08 | | 126 |Biput | s14[1] | | 156 |Biput | reg0A | | 127 |Biput | s14[2] | | 157 |Biput | reg0C | | 128 |Biput | s14[3] | | 158 |Biput | reg0E | | 129 |Biput | NO-CONNECT | | 159 |Vcc | | | 130 |Biput | a32_mode | | 160 |GND | | +-------+------+----------------------+ +-------+------+----------------------+ DEVICE SELECTION: Device Manuf Fam Pack Temp Price User1 User2 1) M5A-128/120-10YC AMD V3.3 QFP COM $ 0.00 0 0 2) M5A-128/120-10YI AMD V3.3 QFP EXT $ 0.00 0 0 3) M5A-128/120-12YC AMD V3.3 QFP COM $ 0.00 0 0 4) M5A-128/120-12YI AMD V3.3 QFP EXT $ 0.00 0 0 5) M5A-128/120-15YI AMD V3.3 QFP EXT $ 0.00 0 0 6) M5A-128/120-5YC AMD V3.3 QFP COM $ 0.00 0 0 7) M5A-128/120-7YC AMD V3.3 QFP COM $ 0.00 0 0 8) M5A-128/120-7YI AMD V3.3 QFP EXT $ 0.00 0 0 9) M5-128/120-15YC AMD CMOS QFP COM $ 15.51 0 0 10) M5-128/120-20YI AMD CMOS QFP EXT $ 16.31 0 0 11) M5-128/120-12YC AMD CMOS QFP COM $ 18.61 0 0 12) M5LV-128/120-12YC AMD V3.3 QFP COM $ 18.61 0 0 13) M5-128/120-15YI AMD CMOS QFP EXT $ 19.58 0 0 PLDocument: Y:\clock\zeus\master\pld1\pld1.doc WIRELIST Mon Nov 15 18:17:13 1999 +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | NO-CONNECT | MV128_120_1 | 129 | | lwordb | MV128_120_1 | 113 | | writeb | MV128_120_1 | 114 | | berrb | MV128_120_1 | 115 | | ds0b | MV128_120_1 | 118 | | ds1b | MV128_120_1 | 119 | | iackb | MV128_120_1 | 112 | | amb[5] | MV128_120_1 | 68 | | amb[4] | MV128_120_1 | 67 | | amb[3] | MV128_120_1 | 66 | | amb[2] | MV128_120_1 | 65 | | amb[1] | MV128_120_1 | 64 | | amb[0] | MV128_120_1 | 63 | | ab[31] | MV128_120_1 | 78 | | ab[30] | MV128_120_1 | 77 | | ab[29] | MV128_120_1 | 76 | | ab[28] | MV128_120_1 | 75 | | ab[27] | MV128_120_1 | 74 | | ab[26] | MV128_120_1 | 73 | | ab[25] | MV128_120_1 | 72 | | ab[24] | MV128_120_1 | 71 | | ab[23] | MV128_120_1 | 110 | | ab[22] | MV128_120_1 | 109 | | ab[21] | MV128_120_1 | 108 | | ab[20] | MV128_120_1 | 107 | | ab[19] | MV128_120_1 | 106 | | ab[18] | MV128_120_1 | 105 | | ab[17] | MV128_120_1 | 104 | | ab[16] | MV128_120_1 | 103 | | ab[15] | MV128_120_1 | 98 | | ab[14] | MV128_120_1 | 97 | | ab[13] | MV128_120_1 | 96 | | ab[12] | MV128_120_1 | 95 | | ab[11] | MV128_120_1 | 94 | | ab[10] | MV128_120_1 | 93 | | ab[9] | MV128_120_1 | 92 | | ab[8] | MV128_120_1 | 91 | | ab[7] | MV128_120_1 | 89 | | ab[6] | MV128_120_1 | 88 | | ab[5] | MV128_120_1 | 87 | | ab[4] | MV128_120_1 | 86 | | ab[3] | MV128_120_1 | 85 | | ab[2] | MV128_120_1 | 84 | | ab[1] | MV128_120_1 | 83 | | dl1 | MV128_120_1 | 33 | | dl2 | MV128_120_1 | 34 | | dl3 | MV128_120_1 | 35 | | base_addr[31] | MV128_120_1 | 30 | | base_addr[30] | MV128_120_1 | 29 | | base_addr[29] | MV128_120_1 | 28 | | base_addr[28] | MV128_120_1 | 27 | +------------------+-------------------+-------+ +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | base_addr[27] | MV128_120_1 | 26 | | base_addr[26] | MV128_120_1 | 25 | | base_addr[25] | MV128_120_1 | 24 | | base_addr[24] | MV128_120_1 | 23 | | base_addr[23] | MV128_120_1 | 18 | | base_addr[22] | MV128_120_1 | 17 | | base_addr[21] | MV128_120_1 | 16 | | base_addr[20] | MV128_120_1 | 15 | | base_addr[19] | MV128_120_1 | 14 | | base_addr[18] | MV128_120_1 | 13 | | base_addr[17] | MV128_120_1 | 12 | | base_addr[16] | MV128_120_1 | 11 | | a32_mode | MV128_120_1 | 130 | | dl0 | MV128_120_1 | 32 | | ack | MV128_120_1 | 39 | | reg[3] | MV128_120_1 | 46 | | reg[2] | MV128_120_1 | 45 | | reg[1] | MV128_120_1 | 44 | | reg[0] | MV128_120_1 | 43 | | reg00 | MV128_120_1 | 151 | | reg02 | MV128_120_1 | 152 | | reg04 | MV128_120_1 | 153 | | reg06 | MV128_120_1 | 154 | | reg08 | MV128_120_1 | 155 | | reg0A | MV128_120_1 | 156 | | reg0C | MV128_120_1 | 157 | | reg0E | MV128_120_1 | 158 | | reg10 | MV128_120_1 | 2 | | reg12 | MV128_120_1 | 3 | | reg14 | MV128_120_1 | 4 | | reg16 | MV128_120_1 | 5 | | reg18 | MV128_120_1 | 6 | | reg1A | MV128_120_1 | 7 | | reg1C | MV128_120_1 | 8 | | reg1E | MV128_120_1 | 9 | | oein | MV128_120_1 | 133 | | oeout | MV128_120_1 | 134 | | le1 | MV128_120_1 | 135 | | nle1 | MV128_120_1 | 136 | | le2 | MV128_120_1 | 137 | | load | MV128_120_1 | 138 | | errorled | MV128_120_1 | 38 | | bwrite | MV128_120_1 | 143 | | bread | MV128_120_1 | 144 | | bwrite_s12 | MV128_120_1 | 56 | | s12[2] | MV128_120_1 | 55 | | s12[1] | MV128_120_1 | 54 | | s12[0] | MV128_120_1 | 53 | | s13[3] | MV128_120_1 | 124 | | s13[2] | MV128_120_1 | 123 | | s13[1] | MV128_120_1 | 58 | +------------------+-------------------+-------+ +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | s13[0] | MV128_120_1 | 57 | | s14[3] | MV128_120_1 | 128 | | s14[2] | MV128_120_1 | 127 | | s14[1] | MV128_120_1 | 126 | | s14[0] | MV128_120_1 | 125 | +------------------+-------------------+-------+