From mp@hep.ucl.ac.uk Mon Jan 19 19:57:20 1998 Date: Mon, 19 Jan 1998 14:53:22 GMT From: "MARTIN POSTRANECKY,UCL-PHYSICS DEP,HEPP GROUP,GOWER ST,LONDON WC1E 6BT,TEL:(00-44)-[0]171-419 3453,FAX:[0]171-380 7145" To: meh@ax8.hep.ucl.ac.uk, mp@ax8.hep.ucl.ac.uk Subject: TC REG. NOTE APPENDIX APPENDICIES : ------------- Z-MTC-1 SETTING - UP LIST =========================== NOTE : All diagram numbers refer to the latest -A- version of CAD FILE TITLE WW1038, Issue A ( WIRE WRAP Z-MTC ) dated AUGUST 1991 Diag.No: Set: ======== ==== 1) 12 Connect all clock links as follows : ------------------------------------ CLK11: DL4/12 to U118/3 CLK13: DL8/3 U118/8 CLK14: DL4/4 DL7/2 DL7/3 U118/4 ( DL9 by-passed ) CLK21: DL6/11 U118/6 CLK23: DL8/1 U118/9 CLK24: DL8/12 U118/7 NCLK2.: DL6/10 U167/1 MTCSTR.:DL4/12 U118/2 ( DL5 by-passed ) P1 to P2 ( PLL 48NSCK ) 2) Set DIL SWITCH SW.1 as follows : -------------------------------- 16 SW.1A P/L CYCLE - OFF - ( Continuous ) 10 SW.1B XTAL CLK - OFF - ( ROC control ) 12 SW.1C CLK SPEED - ON - ( 48 nsec ) 10 SW.1D CLK SELECT - ON - ( ROC control ) This version: MP-UCL, 3 Aug. 1994 Previous versions : 21 Sep. 1993 22 Sep. 1992 Z-LTCC-2 SETTING - UP LIST ============================= NOTE : All diagram numbers refer to the latest -B- version of CAD FILE TITLE WW1035, Issue B ( WIRE WRAP Z-LTCC ) dated NOVEMBER 1991 Diag.No: Set: ======== ==== 1) 14 Connect all clock links as follows : ------------------------------------ CLK11: P12 ( DL5/12 ) to P15 ( U129/3 ) CLK13: P37 ( DL9/12 ) P25 ( U129/8 ) CLK14: * - ( DL5/6 ) * P16 ( DL8/2 ) ----------------- - ( DL8/2 ) P34 ( U183/12) P41 ( DL10/9 ) P27 ( U68/5 ) P29 ( U132/4 ) P42 ( DL10/2 ) CLK21: P20 ( DL7/11 ) P33 ( U129/6 ) CLK23: P39 ( DL9/1 ) P26 ( U129/9 ) CLK24: P37 ( DL9/12 ) P24 ( U129/7 ) NCLK2.: P19 ( DL7/12 ) P32 ( U266/11) MTCSTR.:P14 ( DL5/3 ) P11 ( DL6/2 ) - ( DL6/2 ) P31 ( U129/2 ) NOTE : * indicates the CLK14 link which could be adjusted ====== to correct any Z-CARD Data Transfer timing errors 2) Set DIL SWITCH SW.1 as follows : -------------------------------- 18 SW.1A P/L CYCLE - OFF - ( Continuous ) 12 SW.1B XTAL CLK - OFF - ( ROC control ) 14 SW.1C CLK SPEED - ON - ( 48 nsec ) 12 SW.1D CLK SELECT - ON - ( ROC control ) 3) 09 Set Vth potentiometers P1 - P4 to obtain the following Vth voltage reading on Test Points TP1 - TP4 : (using Digital Multimeter) TP1 : -5.0V TP2 : -5.0V TP3 : -5.0V TP4 : -5.0V This version : MP-UCL, 23 Mar. 1994 Previous versions : 20 Sep. 1993 22 Sep. 1992 14 May 1992 7 Apr. 1992 27 Feb. 1992 18 Feb. 1992 Z-LTCC-3 SETTING - UP LIST ============================ NOTE : All diagram numbers refer to the latest -C- version of CAD FILE TITLE WW1035, Issue C ( WIRE WRAP Z-LTCC ) dated Feb. 1992 Diag.No: Set: ======== ==== 1) 14 Connect all clock links as follows : ------------------------------------ CLK11: LK12/4 ( DL5/12 ) to P2 ( U129/3 ) CLK13: LK16/4 ( DL9/12 ) P9 ( U129/8 ) CLK14: *LK12/9# ( DL5/6# )* P3 ( DL8/2 ) -------------------- LK15/1 ( DL8/2 ) P7 ( U183/12) LK17/7 ( DL10/9 ) P11 ( U68/5 ) P14 ( U132/4 ) P12 ( DL10/2 ) CLK21: LK14/6 ( DL7/11 ) P6 ( U129/6 ) CLK23: LK16/1 ( DL9/1 ) P10 ( U129/9 ) CLK24: LK16/4 ( DL9/12 ) P8 ( U129/7 ) NCLK2: LK14/3# ( DL7/3# ) P5 ( U266/11) MTCSTR.:LK12/2 ( DL5/13 ) P1 ( DL6/2 ) LK13/1 ( DL6/2 ) P4 ( U129/2 ) NOTE: * indicates the CLK14 link which should be adjusted ===== to correct any Z-CARD Data Transfer timing errors Please wire this link on the COMPONENT SIDE of the board # ON LTCC-3/1 ONLY FOR R-BOX-1 USE : ------------------------------------ CLK14 set +10nsec = LK12/11 ( DL5/8 ) NCLK2 set +10nsec = LK14/5 ( DL7/4 ) 2) Connect DIL LINKS LK11 A,B,C,D as follows : --------------------------------------------- 18 LK11A P/L CYCLE - no - ( continuous ) 12 LK11B XTAL CLK - no - ( ROC control ) 14 LK11C CLK SPEED - YES - ( 48 nsec ) 12 LK11D CLK SELECT - YES - ( ROC control ) 3) 09 Set Vth potentiometers P1 - P4 to obtain the following Vth voltage reading on Test Points TP1 - TP4 : ( using digital multimeter ) TP1 : -5.0V TP2 : -5.0V TP3 : -5.0V TP4 : -5.0V This version : MP-UCL, 23 Mar. 1994 Previous versions : 20 Sep. 1993 22 Sep. 1992 14 May 1992 7 Apr. 1992 25 Mar. 1992 5 Mar. 1992 4 Mar. 1992 3 Mar. 1992 Z-LTCC-4 MULTIWIRE BOARDS SETTING-UP LIST ========================================= NOTE : All diagram numbers refer to the latest -A- version of CAD FILE TITLE PC2915M, Issue A ( MULTIWIRE Z-LTCC ) dated Dec. 1991 Diag.No: Set: ======== ==== 1) 14 Connect all clock links as follows : ------------------------------------ CLK11: LK12/4 ( DL5/12 ) to P12 ( U129/3 ) CLK13: LK16/4 ( DL9/12 ) P19 ( U129/8 ) CLK14: *LK12/8 ( DL5/10 )* P13 ( DL8/2 ) -------------------- LK15/1 ( DL8/2 ) P17 ( U183/12) LK17/7 ( DL10/9 ) P21 ( U68/5 ) P24 ( U132/4 ) P22 ( DL10/2 ) CLK21: LK14/6 ( DL7/11 ) P16 ( U129/6 ) CLK23: LK16/1 ( DL9/1 ) P20 ( U129/9 ) CLK24: LK16/4 ( DL9/12 ) P18 ( U129/7 ) NCLK2: LK14/3 ( DL7/3 ) P15 ( U266/11) MTCSTR.:LK12/2 ( DL5/13 ) P11 ( DL6/2 ) LK13/1 ( DL6/2 ) P14 ( U129/2 ) NOTE: * indicates the CLK14 link which should be adjusted ===== to correct any Z-CARD Data Transfer timing errors 2) Connect DIL LINKS LK11 A,B,C,D as follows : --------------------------------------------- 18 LK11A P/L CYCLE - no - ( continuous ) 12 LK11B XTAL CLK - no - ( ROC control ) 14 LK11C CLK SPEED - YES - ( 48 nsec ) 12 LK11D CLK SELECT - YES - ( ROC control ) 3) 09 Set Vth potentiometers P1 - P4 to obtain the required Vth voltage reading on Test Points TP1 - TP4 ( using digital multimeter ) TP1 : -5.0V TP2 : -5.0V TP3 : -5.0V TP4 : -5.0V This version : MP-UCL, 23 Mar. 1994 Previous versions : 20 Sep. 1993 22 Sep. 1992 13 May 1992 12 May 1992 27 Apr. 1992 5 Mar. 1992 4 Mar. 1992 3 Mar. 1992 Z-LTCC-5 MULTIWIRE BOARDS SETTING-UP LIST ========================================= NOTE : All diagram numbers refer to the latest -B- version of CAD FILE TITLE PC2915M, Issue B ( MULTIWIRE Z-LTCC ) dated Sept. 1992 Diag.No: Set: ======== ==== 1) 14 Connect all clock links as follows : ------------------------------------ CLK11: LK12/4 ( DL5/12 ) to P12 ( U129/3 ) CLK13: LK16/4 ( DL9/12 ) P19 ( U129/8 ) CLK14: LK12/10 ( DL5/9 )*#% P13 ( DL8/2 ) -------------------- LK15/1 ( DL8/2 ) P17 ( U130/1 ) LK17/7 ( DL10/9 )% P21 ( U68/9 ) P24 ( U132/4 )% P22 ( DL10/2 ) CLK21: LK14/6 ( DL7/11 ) P16 ( U129/6 ) CLK23: LK16/1 ( DL9/1 ) P20 ( U129/9 ) CLK24: LK16/4 ( DL9/12 ) P18 ( U129/7 ) NCLK2: LK14/5 ( DL7/4 )#% P15 ( U128/13) MTCSTR.:LK12/2 ( DL5/13 ) P11 ( DL6/2 ) LK13/1 ( DL6/2 ) P14 ( U129/2 ) NOTES: * indicates the CLK14 link which should be adjusted ====== to correct any Z-CARD Data Transfer timing errors # ON LTCC-5/1 ONLY, FOR RBOX-1 USE : ================================== CLK14 set +13nsec ( = -35ns ) = LK12/3 ( DL5/3 ) NCLK2 set +10nsec = LK14/7 ( DL7/5 ) % ON LTCC-5/2 ONLY, FOR RBOX-2 & Z-CARD USE : =========================================== CLK14 set +18nsec ( = -30ns ) = LK12/4 ( DL5/12) NCLK2 set +10nsec = LK14/7 ( DL7/5 ) CLK14 set width +9nsec = LK17/11 ( DL10/13) = P25 ( U132/16) 2) Connect DIL LINKS LK11 A,B,C,D as follows : --------------------------------------------- 18 LK11A P/L CYCLE - no - ( continuous ) 12 LK11B XTAL CLK - no - ( ROC control ) 14 LK11C CLK SPEED - YES - ( 48 nsec ) 12 LK11D CLK SELECT - YES - ( ROC control ) 3) 09 Set Vth potentiometers P1 - P4 to obtain the required Vth voltage reading on Test Points TP1 - TP4 ( using digital multimeter ) TP1 : -5.0V TP2 : -5.0V TP3 : -5.0V TP4 : -5.0V This version : MP-UCL, 18 Aug. 1994 Previous versions : 3 Aug. 1994 23 Mar. 1994 20 Sep. 1993 Z-LTCC-6 & 7 MULTIWIRE BOARDS SETTING-UP LIST ============================================= NOTE : All diagram numbers refer to the latest -C- version of CAD FILE TITLE PC2915M, Issue C ( MULTIWIRE Z-LTCC ) dated Oct. 1993 Diag.No: Set: ======== ==== 1) 14 Connect all clock links as follows : ------------------------------------ CLK11: LK12/4 ( DL5/12 ) to P12 ( U129/3 ) CLK13: LK16/4 ( DL9/12 ) P19 ( U129/8 ) CLK14: *LK12/10 ( DL5/9 )* P13 ( DL8/2 ) -------------------- LK15/1 ( DL8/2 ) P17 ( U130/1 ) LK17/7 ( DL10/9 ) P21 ( U68/5 ) P24 ( U132/4 ) P22 ( DL10/2 ) CLK21: LK14/6 ( DL7/11 ) P16 ( U129/6 ) CLK23: LK16/1 ( DL9/1 ) P20 ( U129/9 ) CLK24: LK16/4 ( DL9/12 ) P18 ( U129/7 ) NCLK2: LK14/5 ( DL7/4 ) P15 ( U128/13) MTCSTR.:LK12/2 ( DL5/13 ) P11 ( DL6/2 ) LK13/1 ( DL6/2 ) P14 ( U129/2 ) NOTE: * indicates the CLK14 link which should be adjusted ===== to correct any Z-CARD Data Transfer timing errors 2) Connect DIL LINKS LK11 A,B,C,D as follows : --------------------------------------------- 18 LK11A P/L CYCLE - no - ( continuous ) 12 LK11B XTAL CLK - no - ( ROC control ) 14 LK11C CLK SPEED - YES - ( 48 nsec ) 12 LK11D CLK SELECT - YES - ( ROC control ) 3) 09 Set Vth potentiometers P1 - P4 to obtain the required Vth voltage reading on Test Points TP1 - TP4 ( using digital multimeter ) TP1 : -5.0V TP2 : -5.0V TP3 : -5.0V TP4 : -5.0V This version : MP-UCL, 23 Mar. 1994 Previous versions : 20 Sep. 1993 Cabling Check List for Mickey Mouse or Piglet Mouse JBL 11-Apr-1992 =================================================== Mickey Mouse is the MMTC and Piglet Mouse is the Prototype MTC. BUSY cables (black) ----------- The MMTC has 4 BUSY inputs, and use inputs 1 to 4 of the MTC. Connect the required BUSY cables into the front panel connectors. Pull down unused BUSY inputs by 50 ohms. At present the software enables the first 4 BUSY inputs of the MTC and the remaining BUSY inputs are disabled. CHECK that the BUSY inputs are only the crates in use. Clock cables (white) ------------ The MMTC has 4 clock outputs, and the MTC has 8 (use any). Connect the clock cables into the front panel connectors. Ribbon cables ------------- Connect the ribbon cables as follows : Connector Cable MMTC MTC 40-way MTC-LTC Bus A ../P5a/.. Front Lower front 40-way MTC-LTC Bus B ../P5b/.. Next in Upper front 34-way MTC Control RBOX CONT (GFLT P01) Rear Top behind The following come from the FANOUTs to both and can be left : 34-way GFLT Clock (GFLT P05) 34-way GFLT Control (GFLT P04) 34-way GFLT Number (GFLT P03) Daisy-chain ----------- For the MMTC, the daisy-chain of 40-way cables should be terminated at the last LTCC in use (e.g. third or fourth), because of Buffers Full. With the MTC, the termination can be left at the end (fourth LTCC) because the BUSYs do all the handshaking. ZEUS02::disk$online:[Lane.TC]MTCcable.TXT MTC LED Description JBL 14-Apr-1992 =================== Layout of LEDs for MTC-1 ------------------------ * DS.01 Trigger * DS.03 Nline * DS.02 Abort * DS.04 Interrupt g DS.05 +5V supply DS.13 BCN0 Fault g DS.06 -5V2 supply DS.14 Clock Fault * DS.07 Error DS.15 Command Fault * DS.08 Initialise * DS.16 Next Buffer Full * DS.09 Test Enable DS.17 LTC BCN0 Fault DS.10 Pause Mode DS.18 LTC Clock Fault DS.11 ROC Pipeline Freeze DS.19 LTC Reset DS.12 End Of Run DS.20 PLL Fault DS.21 MTC BUSY DS.29 BUSYA - MTC Accept DS.22 Stand By y DS.30 XTAL clock running DS.23 Available y DS.31 GFLT clock running DS.24 Initialise DS.32 Pipeline running DS.25 Ready DS.33 Copy running DS.26 Accept DS.34 ROC in Control DS.27 BUSYS - MTC Stand By DS.35 GFLT in Control DS.28 BUSYI - MTC Initialise DS.36 LTC BUSY Notes ----- 1. LEDs marked * have an extended flash so a single pulse can be seen. DS.01, DS.02, DS.03, DS.04 have a short extended flash. DS.07, DS.08, DS.09, DS.16 have a longer extended flash. 2. DS.01, DS.02, DS.08, DS.09 show the commands output to the LTCCs. 3. DS.10, DS.11, DS.12 show when the system is in a special state. 4. DS.13 - DS.20 show the Control Status register Fault bits. Once on they stay on until cleared by the ROC (or RESET or start of Run), except DS.16 Next Buffer Full (unlike the CSR bit). 5. DS.21 - DS.36 show the Current State register bits. The more important MTC LEDs --------------------------- DS.01 Trigger Trigger is output to the LTCs. DS.03 Nline MTC is addressed by the ROC. DS.07 Error Error is caused by Command Fault, Timeout, RESET, entering Stand By, or is set by the ROC. Fatal Error sent to GFLT. DS.16 Next Buffer Full An LTC has Next Buffer Full (but can accept a Trigger if BUSY off). DS.20 PLL FAULT The 96nsec-to-48nsec PLL has lost its lock. DS.21 MTC BUSY BUSY output to GFLT. Always on under ROC Control. BUSY off means ready for FLT Accept (Initialise or Trigger) from GFLT. DS.23 Available Available for Run and waiting for Initialise. DS.25 Ready Ready and waiting for Trigger. DS.26 Accept BUSY while accepting an event after Trigger. DS.30 XTAL clock running (selected if not GFLT in Control). DS.31 GFLT clock running (selected only if GFLT in Control). DS.34 ROC in Control Internal XTAL clock and ROC commands are output to LTCCs. DS.35 GFLT in Control External GFLT clock and GFLT signals are output to LTCCs. DS.36 LTC BUSY An (enabled) LTC is BUSY : the OR of the enabled LTC BUSY inputs. Enabled but unused BUSY inputs must be pulled down by 50 ohms (or less). ZEUS02::disk$online:[Lane.TC]MTCLEDs.TXT LTC LED Description JBL 14-Apr-1992 =================== Layout of LEDs for Z-LTCC-2 --------------------------- g DS.01 +5V supply g DS.03 -10V supply g DS.02 -5V2 supply g DS.04 Transfer DS.05 LCC - No Reply DS.17 BCN0 Fault DS.06 LCC - Ready DS.18 Clock Fault * DS.07 Nline y DS.19 XTAL clock running * DS.08 Interrupt y DS.20 MTC clock running y DS.09 Pause Mode DS.21 Pipeline running DS.10 LTC BUSY DS.22 Copy running DS.11 Stand By g DS.23 ROC in Control DS.12 Available DS.24 MTC in Control DS.13 Initialise DS.25 MTC Request DS.14 Ready (Pipeline Control) DS.26 Wait for Valid DS.15 Copy Pipeline DS.27 Wait for ROC DS.16 Wait for Buffer DS.28 RESET Notes ----- 1. LEDs marked * have an extended flash so a single pulse can be seen. DS.07, DS.08 have a short extended flash. 2. DS.05, DS.06 are Calibration Controller LEDs. 3. DS.17, DS.18 show the Control Status register Fault bits. Once on they stay on until cleared by the ROC (or RESET or start of Run). 4. DS.10 - DS.16, DS.26, DS.27, DS.19 - DS.25 show the Current State register bits. 5. g = green LED y = yellow LED = red LED Layout of LEDs for Z-LTCC-3,4,5,6 & 7 ------------------------------------- LABEL: NO: FUNCTION: LABEL: NO: FUNCTION: ------------------------------------------------------------------------- N1 * DS.01 Nline TR * DS.03 Transfer IN * DS.02 Interrupt RC * DS.04 RESET +5 g DS.05 +5V supply PL DS.17 Ready (Pipeline Control) -5 g DS.06 -5V2 supply CP DS.18 Copy Pipeline -10 g DS.07 -10V supply BF DS.19 Wait for Buffer NR y DS.08 LCC - No Reply VA DS.20 Wait for Valid RE y DS.09 LCC - Ready RO DS.21 Wait for ROC B0 DS.10 BCN0 Fault XC y DS.22 XTAL clock running CL DS.11 Clock Fault MC y DS.23 MTC clock running PA y DS.12 Pause Mode PO DS.24 Pipeline running LB DS.13 LTC BUSY CO DS.25 Copy running ST DS.14 Stand By RC DS.26 ROC in Control AV DS.15 Available MC DS.27 MTC in Control IN DS.16 Initialise MR DS.28 MTC Request Notes ----- 1. LEDs marked * have an extended flash so a single pulse can be seen. DS.01, DS.02, DS.03, DS.04 have a short extended flash. 2. DS.08, DS.09 are Calibration Controller LEDs. 3. DS.10, DS.11 show the Control Status register Fault bits. Once on they stay on until cleared by the ROC (or RESET or start of Run). 4. DS.13 - DS.28 show the Current State register bits. 5. g = green LED y = yellow LED = red LED The more important LTC LEDs --------------------------- Nline LTC is addressed by the ROC. Interrupt LTC is asserting the Interrupt line. Transfer LTC is asserting the Transfer line. LTC BUSY BUSY output to MTC. Always on under ROC Control. BUSY off means ready for FLT Accept (Initialise or Trigger) from MTC. Available Available for Run and waiting for Initialise. Ready (Pipeline Control) Ready and waiting for Trigger. Wait for Buffer BUSY waiting for the next buffer to be freed by the ROC. Wait for Valid Waiting for deassertion of Trigger to validate event buffer, or for Abort. Wait for ROC BUSY waiting for the ROC to clear End Of Run or ROC Pipeline Freeze. XTAL clock running (selected if not MTC in Control). MTC clock running (selected only if MTC in Control). ROC in Control Internal XTAL clock and ROC commands are used. MTC in Control External MTC clock and MTC commands are used. ZEUS02::disk$online:[Lane.TC]LTCLEDs.TXT DIAGNOSTICS CONNECTORS ON THE FRONT PANEL OF Z-LTCCs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1) DIAGNOSTICS CONNECTOR J31 PIN-OUT : ===================================== A) FOR Z-LTCC-3s WIRE-WRAPS AND -4s, -5s MULTIWIRE ----------------------------------------------- 1 LTCBUSYOUT 2 ST(1) 3 ST(2) 4 ST(3) 5 ST(4) 6 ST(5) 7 ST(6) 8 ST(7) 9 ST(8) 10 ST(9) 11 CURSTATE9 12 CURSTATE10 13 CURSTATE11 14 CURSTATE12 15 CURSTATE13 16 CURSTATE14 17 * WRITEFAULT * 18 NLINE1 19 NMEMEN 20 NWRITE 21 NTRANSFEROUT 22 NBCN0OUT 23 NINTERRUPT OUT 24 BUFFULL 25 BUFFERFULLINPUT 26 FLTACCEPT 27 INITIALISE 28 ABORT 29 EORIN 30 ROCPLFRIN 31 BCN0IN 32 TENABLE 33 CLK1 34 MTCSTROBECLK 35 CLK11 36 CLK14 37 NCLK2OUT 38 CLK24 39 CLK13 40 10MHz CLK 41 PA(0) 42 DPA(0) 43 INTBUSY 44 NZERO RESET 45 NZERO RESET2 46 NZERO RESET4 47 NCLR1 48 INHIBIT COUNT1 49 INHIBIT COUNT3 50 TESTENABLE NOTE: * WRITEFAULT * NOT AVAILABLE ON LTCC-3s & 4s ===================================================== /cont./ - 2 - B) FOR Z-LTCC-6s & -7s MULTIWIRE ----------------------------- 1 LTCBUSYOUT 2 ST(1) 3 ST(2) 4 ST(3) 5 ST(4) 6 ST(5) 7 ST(6) 8 ST(7) 9 ST(8) 10 ST(9) 11 CURSTATE9 12 CURSTATE10 13 CURSTATE11 14 CURSTATE12 15 CURSTATE13 16 CURSTATE14 17 WRITEFAULT 18 NLINE1 19 NMEMEN 20 NWRITE 21 NTRANSFEROUT 22 NBCN0 23 NINTERRUPT OUT 24 BUFFULL 25 BUFFERFULLINPUT 26 FLTACCEPT 27 INITIALISE 28 ABORT 29 EORIN 30 ROCPLFRIN 31 BCN0IN 32 TENABLE 33 BCLK1 34 BMTCSTROBECLK 35 BCLK11 36 BCLK14 37 BNCLK2OUT 38 BCLK24 39 BCLK13 40 B10MHz CLK 41 BPA(0) 42 BDPA(0) 43 INTBUSY 44 NZERO RESET 45 NZERO RESET2 46 NZERO RESET4 47 NCLR1 48 INHIBIT COUNT1 49 INHIBIT COUNT3 50 TESTENABLE 2) TEST POINTS TP2 ON LEDs PCB : ================================== ON Z-LTCC-6s and -7s MULTIWIRE ONLY : ------------------------------------ 1 CLK48 CLK14 ( 48nsec strobe clock ) fed back onto LTCC via the backplane twisted pair loom as ECL and re-converted to TTL 2 BNCLK2OUT 96nsec clock 3 BPA(0) RA(0)= PLM lsb address 4 BDPA(0) DA(0)= DPM lsb address All buffered TTL signals, with same timing as on backplane This version : MP-UCL, 3 Aug. 1994 Previous versions : 22 Mar. 1994 21 Mar. 1994 10 Mar. 1994 9 Nov. 1993 20 Oct. 1993 17 Sep. 1993 13 Sep. 1993 19 Nov. 1992 12 May. 1992 30 Mar. 1992