UCL Zeus Z System Test Suite - TCT

Technical Contents
What does it do?
TCT (Timing Controller Test)
This is a simple register and buffer-loop test for either an LTC or an MTC. (for details see below)
TCCC (Timing Controller Continous Copy test) NO INFO
This is a simple interrupt clearing loop for an LTC under MTC control. (Uses an MTC and an LTC in the same crate, though the MTC is not essential)
SST (Simple System Test) OBSOLETE
This is a test that uses both an MTC and an LTC in the same crate. It loads a reference pattern into the MTC dpminfo registers and produces triggers. The LTC runs under MTC control. The contents of the LTC dpminfo registers are compared with the original contents of the MTC dmpminfo registers after each trigger.
TCTA: (Timing Controller Trigger Address test) NO INFO
This test is still under development. It is intended to work in a similar manner to SST, but checking the trigger address against the BCN, assuming this has been correctly passed down from the GFLTB.
Unfortunately the only separate documentation is for TCT and is a little out of date (there is now a register loop test option to start with).
What are the loop tests?

TCT provides a choice of loop test options. In each case the ZLTC is initialised and then cycled round a given number of trigger loops, the software each time performing various checks and resets. Errors are communicated to the error-reporting process (emu_to_vax on the ROC transputer), and accumulated in counters which are displayed by TCT at the end of the loop test.

The current loop test options are: (this list is incomplete)
Buffer Cycle Loop test
In this test all "DPM valid" bits which have been set are cleared before the next trigger command is issued. After a trigger command has been issued the program waits for the "copy complete" bit to be set in the ZLTC interrupt register before clearing any set "DPM valid" bits and issuing the next trigger command.
Buffer Interrupt Loop test
This test is like the Buffer Cycle Loop test above, except that the program waits for an interrupt to be received at the ROC transputer from the ZLTC, rather than waiting for the "copy complete" bit to be set in the ZLTC interrupt register.
Buffer Full Loop test
In this test the "DPM valid" bits are NOT cleared after after each trigger. This means that when all ten DPM buffers have been used the "buffers full" bit should become set in the ZLTC Control Status register. The program checks that this bit has been set at the appropriate stage before going on to clear the "DPM valid" bits ready for another cycle round the DPM buffers.

The detailed sequence is rather complicated, and the first cycle is different from subsequent ones. On the first cycle buffers 0 to 8 are filled by the first 9 triggers. The 10th trigger initiates a copy to the 10th buffer (i.e. buffer 9), but the "DPM valid 9" bit will not be set in the ZLTC interrupt register until the "copy complete" bit is set, which won't happen whilst there are no further free buffers (this prevents the ZLTC getting a trigger when there is no free buffer to copy into). So the ZLTC_TEST program has to perform its "buffers full" check after the 10th trigger, but before the "copy complete" bit is set. This means that when the "DPM valid" bits are all cleared down after the "buffers full" check the "copy complete" bit will become set and the "DPM valid 9" bit will be set for the 10th buffer. Consequently the next cycle will start with only 9 free buffers instead of the 10 that were free for the first cycle. Thus the "buffers full" check will now have to be performed after the 9th subsequent trigger. Again, when the "DPM valid" bits have been cleared down after the check, there will be an outstanding copy to complete and the associated "DPM valid" bit will get set. The buffer number of this bit will steadily decrease with each cycle over the buffers (wrapping back to 9 after it has reached 0), but the number of free buffers at the beginning of each cycle will stay at 9 for every cycle after the first (for which there are 10 free buffers).
What do the errors mean?

Several different types of error are checked for in the transputer process "test.ltc". On the occurrence of an error a message is sent to the process "emu.to.vax" and the appropriate error counter is incremented inside "test.ltc". At the end of the chosen test, "test.ltc" sends all the error counters to ZLTC_TEST as a block, where they are then output (to LUN 6).

The current counter offsets in the error-counter block are as follows:
[00] E.ERROR ......... UNCATEGORISED ERROR
any error number greater than the highest known error number is logged in this counter.

[01] E.BC.NOSAME ..... BUFFER COUNT DIFFERENT FROM "LAST" VALUE
the buffer count is checked after the trigger command has been given, but before the "event" has been validated: the buffer count should be unchanged.

[02] E.IR.NOSAME ..... INTERRUPT REGISTER DIFFERENT FROM "LAST" VALUE
the interrupt register is checked after the trigger command has been given, but before the "event" has been validated: the interrupt register should be unchanged.

[03] E.BC.NONEXT ..... BUFFER COUNT DIFFERENT FROM "NEXT" VALUE
the buffer count is checked after the trigger command bit has been cleared, i.e. after the "event" has been validated: the buffer count should have incremented (cyclically).

[04] E.IR.NONEXT ..... INTERRUPT REGISTER DIFFERENT FROM "NEXT" VALUE
the interrupt register is checked after the trigger command bit has been cleared, i.e. after the "event" has been validated: the next (cylic) interrupt bit should be set.

[05] E.BW.NOSET ...... ZLTC NOT IN "WAIT FOR BUFFER" STATE (WHEN IT SHOULD BE)
in the buffers full loop test, the ZLTC should have the "wait for buffer" bit set in the current state register when all the buffers have been used, but before the "DPM valid" bits have been cleared.

[06] E.BW.SET ........ ZLTC IN "WAIT FOR BUFFER" STATE (WHEN IT SHOULD NOT BE)
in the "buffers full" loop test, the ZLTC should have the "wait for buffer" bit cleared in the current state register once the "DPM valid" bits have been cleared.

[07] E.INT.TIMEOUT ... NO INTERRUPT RECEIVED WITHIN PROGRAMMED INTERVAL
in the buffer interrupt loop test, the test.ltc program waits for an interrupt from the ZLTC rather than polling the "copy complete" flag in the ZLTC interrupt register. The interrupt should normally already be set by the time it is waited for, since it will have taken some time to execute the several Occam instructions that comprise the checking code that follows the setting of the trigger command bit. To make sure, the timeout interval is set to one transputer "tick" (approx. 64 microseconds) which should allow plenty of time for a normal length event to be copied.

[08] E.BAD.COPYLEN ... END COPY ADDRESS DIFFERENT FROM EXPECTED VALUE
the expected end copy address can always be calculated since the trigger address, copy length, and pipeline length are all known.

[09] E.BAD.REG ....... REGISTER DOES NOT CONTAIN EXPECTED PATTERN
the register tests write various patterns to the ZLTC registers and check that they have been written successfully.
A Diagram of ZLTC_TEST process interaction: 
  +++++++++++                                               +++++++++++
  + LUN 6   +<--.                                       .-->+ LUN 6   +
  +++++++++++   |                                       |   +++++++++++
                |                                       |   +++++++++++
                |                                       |-->+ LUN 10  +
                |                                       |   +++++++++++
                |                                       |
    ************************                 ************************
    *                      *                 *                      *
    *   LTC_TEST           *                 *    EMU_FROM_ROC      *
    *                      *                 *                      *
    ************************                 ************************
                    ^  |  |                    ^  |  |
                    |  |  |                    |  |  |
               *****************************************  
               *    |  |  |                    |  |  | *   +++++++++++++
               *    |  |  .--------------------|--|--.-*-->+ debug LUN +
               *    |  |                       |  |    *   +++++++++++++
               *    |  |  HARNESS (VAX)        |  |    *               
               *****************************************
                    |  |                       |  |
  VAX               |  |                       |  |
  ................. :..:.......................:..:.....................
  ROC transputer    |  |                       |  |
                    |  |                       |  |
               *****************************************
               *    |  |                       |  |    *
               *    |  |                       |  |    *
               *    |  |  HARNESS (transputer) |  |    *
               *****************************************
                    |  |                       |  |
                    |  v                       |  v
    ************************                 ************************
    *                      *                 *                      *
    *    test.ltc          * --------------->*   emu.to.vax         *
    *                      *  error messages *                      *
    ************************                 ************************
Key: 
      *******             ++++++                           | ^
      *     * = process   +    + = output LUN/window   --> | | = data flows
      *******             ++++++                           v |